ERROR-CHECKING IN NAMESPACES ON STORAGE DEVICES USING A NAMESPACE TABLE AND METADATA

• US 20200133849A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Harris, Byron D., Schuh, Karl D.
• Granted Patent: US 10,691,592 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.

Claims

1. A computer-implemented method comprising:

identifying a namespace identifier for a namespace associated with a first write instruction received from a host process, wherein the first write instruction includes data and a first namespace offset;

generating a first logical address by combining the namespace identifier and the first namespace offset;

translating the first logical address to a first physical address using a plurality of hierarchical tables, wherein the plurality of hierarchical tables includes a namespace table and one or more translation tables;

generating a second write instruction, wherein the second write instruction includes the data, the first physical address, and the first logical address; and

sending the second write instruction to a memory component, wherein the memory component stores the data at the first physical address and wherein the memory component stores the first logical address, including the namespace identifier, as metadata associated with the data.

2. The method of claim 1, further comprising:

receiving a first read instruction from the host process, wherein the first read instruction includes a second namespace offset;

identifying the namespace identifier for the namespace assigned to the host process;

generating a second logical address by combining the namespace assigned to the host process and the second namespace offset;

translating the second logical address to a second physical address using the plurality of hierarchical tables;

generating a second read instruction, wherein the second read instruction includes the second physical address and the second logical address; and

sending the second read instruction to the memory component, wherein the memory component validates the translation of the second logical address by comparing the second logical address in the second read instruction to the metadata associated with the data to be read at the second physical address.

3. The method of claim 1, wherein the namespace table includes one or more namespace entries and wherein each namespace entry includes a starting location in a first translation table in the one or more translation tables and a size of the namespace in the first translation table.

4. The method of claim 1, wherein combining the namespace identifier and the first namespace offset includes appending the first namespace offset to the namespace identifier.

5. The method of claim 1, wherein translating the first logical address includes locating an entry in the namespace table using the namespace identifier.

6. The method of claim 1, wherein the metadata is stored in a reserved portion of the memory component associated with the first physical address.

7. The method of claim 1, further comprising:

adding a new entry to the namespace table in response to an instruction from the host process to create a new namespace.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

identifying a namespace identifier for a namespace associated with a first write instruction received from a host process, wherein the first write instruction includes data and a first namespace offset;

generating a first logical address by combining the namespace identifier and the first namespace offset;

translating the first logical address to a first physical address using a plurality of hierarchical tables, wherein the plurality of hierarchical tables includes a namespace table and one or more translation tables;

generating a second write instruction, wherein the second write instruction includes the data, the first physical address, and the first logical address; and

sending the second write instruction to a memory component, wherein the memory component stores the data at the first physical address and wherein the memory component stores the first logical address, including the namespace identifier, as metadata associated with the data.

9. The non-transitory computer-readable storage medium of claim 8, wherein the instructions, when executed cause the processing device to perform operations comprising:

receiving a first read instruction from the host process, wherein the first read instruction includes a second namespace offset;

identifying the namespace identifier for the namespace assigned to the host process;

generating a second logical address by combining the namespace assigned to the host process and the second namespace offset;

translating the second logical address to a second physical address using the plurality of hierarchical tables;

generating a second read instruction, wherein the second read instruction includes the second physical address and the second logical address; and

sending the second read instruction to the memory component, wherein the memory component validates the translation of the second logical address by comparing the second logical address in the second read instruction to the metadata associated with the data to be read at the second physical address.

10. The non-transitory computer-readable storage medium of claim 8, wherein the namespace table includes one or more namespace entries and wherein each namespace entry includes a starting location in a first translation table in the one or more translation tables and a size of the namespace in the first translation table.

11. The non-transitory computer-readable storage medium of claim 8, wherein combining the namespace identifier and the first namespace offset includes appending the first namespace offset to the namespace identifier.

12. The non-transitory computer-readable storage medium of claim 8, wherein translating the first logical address includes locating an entry in the namespace table using the namespace identifier.

13. The non-transitory computer-readable storage medium of claim 8, wherein the metadata is stored in a reserved portion of the memory component associated with the first physical address.

14. The non-transitory computer-readable storage medium of claim 8, wherein the instructions, when executed cause the processing device to perform operations comprising:

adding a new entry to the namespace table in response to an instruction from the host process to create a new namespace.

15. A system comprising:

a memory component; and

a processing device, coupled to the memory component, configured to;

identify a namespace identifier for a namespace associated with a first write instruction received from a host process, wherein the first write instruction includes data and a first namespace offset;

generate a first logical address by combining the namespace identifier and the first namespace offset;

translate the first logical address to a first physical address using a plurality of hierarchical tables, wherein the plurality of hierarchical tables includes a namespace table and one or more translation tables;

generate a second write instruction, wherein the second write instruction includes the data, the first physical address, and the first logical address; and

send the second write instruction to the memory component, wherein the memory component stores the data at the first physical address and wherein the memory component stores the first logical address, including the namespace identifier, as metadata associated with the data.

16. The system of claim 15, wherein the processing device is further configured to:

receive a first read instruction from the host process, wherein the first read instruction includes a second namespace offset;

identify the namespace identifier for the namespace assigned to the host process;

generate a second logical address by combining the namespace assigned to the host process and the second namespace offset;

translate the second logical address to a second physical address using the plurality of hierarchical tables;

generate a second read instruction, wherein the second read instruction includes the second physical address and the second logical address; and

send the second read instruction to the memory component, wherein the memory component validates the translation of the second logical address by comparing the second logical address in the second read instruction to the metadata associated with the data to be read at the second physical address.

17. The system of claim 15, wherein the namespace table includes one or more namespace entries and wherein each namespace entry includes a starting location in a first translation table in the one or more translation tables and a size of the namespace in the first translation table.

18. The system of claim 15, wherein combining the namespace identifier and the first namespace offset includes appending the first namespace offset to the namespace identifier.

19. The system of claim 15, wherein translating the first logical address includes locating an entry in the namespace table using the namespace identifier.

20. The system of claim 15, wherein the metadata is stored in a reserved portion of the memory component associated with the first physical address.