Apparatus and Method to Access a Memory Location

• US 20200133850A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Chong, Yew Keong, Thyagarajan, Sriram, Chen, Andy Wangkun
• Granted Patent: US 10,817,420 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1016 Performance improvement

Abstract

A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.

Claims

1. A method, comprising:

determining a first set of address bits common to an address of a first memory location and to an address of a second memory location in a memory macro;

determining a second set of address bits of the address of the first memory location;

determining a third set of address bits of the address of the second memory location; and

concatenating the first, second, and third sets of address bits to a single bit string.

2. The method of claim 1, wherein the first and second sets of address bits identify a first wordline of the first memory location, and the first and third sets of address bits identify a second wordline of the second memory location.

3. The method of claim 1, wherein the first memory location is within a first memory array, and the second memory location is within a second memory array that is different from the first memory array.

4. The method of claim 1, wherein the third set of address bits is identical to the second set of address bits.

5. The method of claim 1, wherein the third set of address bits is different from the second set of address bits.

6. The method of claim 1, wherein a number of bits of the third set of address bits is equal to a number of bits of the second set of address bits.

7. The method of claim 6, wherein a number of bits of the first set of address bits is greater than the number of bits of the third set of address bits.

8. The method of claim 1, further comprising communicating the single bit string to an address bus.

9. The method of claim 8, wherein the address bus has a number of bus lines no greater than a sum of a number of bits of the first set of address bits, a number of bits of the second set of address bits, and a number of bits of the third set of address bits.

10. A method, comprising:

receiving an address string;

determining, from the address string, a first address of a first wordline in a first memory array of a memory macro; and

determining, from the address string, a second address of a second wordline in a second memory array of the memory macro.

11. The method of claim 10, further comprising:

retrieving data bits from a first memory location in the first memory array, wherein the first memory location corresponds to the first wordline; and

retrieving data bits from a second memory location in the second memory array, wherein the second memory location corresponds to the second wordline.

12. The method of claim 10, further comprising:

parsing the address string to;

determine the first address of the first wordline, and

determine the second address of the second wordline.

13. The method of claim 12, wherein:

determining the first address of the first wordline comprises concatenating a first set of bits of the address string with a second set of bits of the address string; and

determining the second address of the second wordline comprises concatenating the first set of bits of the address string with a third set of bits of the address string.

14. The method of claim 13 wherein the third set of bits is different from the second set of bits.

15. The method of claim 10, further comprising:

reading data from a first memory location that corresponds to the first wordline; and

reading data from a second memory location that corresponds to the second wordline.

16. An apparatus, comprising:

an address decoder configured to;

receive an address string,

parse the address string into a first address of a first wordline in a first memory array, and

parse the address string into a second address of a second wordline in a second memory array; and

a wordline driver section of a memory macro, wherein the wordline driver section is electrically coupled to the address decoder and configured to;

receive the first address of the first wordline, and

receive the second address of the second wordline.

17. The apparatus of claim 16, further comprising:

an address data processing unit; and

an address bus electrically coupled to the address decoder and to the address data processing unit, and

wherein the address data processing unit is configured to;

determine a first set of bits that are common to an address of a first memory location and to an address of a second memory location in a memory macro;

determine a second set of bits of the address of the first memory location;

determine a third set of bits of the address of the second memory location; and

concatenate the first, second, and third sets of address bits to form the address string.

18. The apparatus of claim 17, wherein the first and second sets of bits identify the first wordline, and the first and third sets of bits identify the second wordline.

19. The apparatus of claim 17, wherein the third set of bits is different from the second set of bits.

20. The apparatus of claim 17, wherein the third set of bits is the same as the second set of bits.