METHODS AND SYSTEMS FOR MANAGING SYNONYMS IN VIRTUALLY INDEXED PHYSICALLY TAGGED CACHES

• US 20200133861A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Avudaiyappan, Karlhikeyan
• Granted Patent: US 11,314,647 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.

Claims

1. A method of managing virtual address synonyms in a virtually indexed physically tagged (VIPT) cache, comprising:

receiving an access request to a VIPT cache that is associated with a first virtual address having a synonym virtual address (VA) bit that is the same as a synonym VA bit of a second virtual address associated with a previously received access request;

predicting a value of a bit of a physical address associated with said first virtual address in advance of determining the actual value of the bit of the physical address;

determining an actual value of the bit of the physical address;

providing an indication of a miss and updating a predictor, in response to the predicted value of the bit of the physical address provided in advance being different from the actual value of the bit of the physical address; and

retrying the access request using the actual value of the bit of the physical address.

2. The method of claim 1, wherein the first virtual address and the second virtual address are associated with separate processes.

3. The method of claim 1, wherein different physical addresses are associated with the first virtual address and the second virtual address.

4. The method of claim 1, wherein a same physical address is associated with the first virtual address and the second virtual address.

5. The method of claim 1, wherein the first virtual address is in a first cache line of the VIPT cache and the second virtual address is in a second cache line of the VIPT cache.

6. The method of claim 5, wherein the first cache line is in a first panel of the VIPT cache and the second cache line is in a second panel of the VIPT cache.

7. The method of claim 6, wherein a first value of the VA bit is associated with the first panel and a second value of the VA bit is associated with the second panel.

8. A cache memory system, comprising:

memory components; and

a memory controller, wherein said memory controller includes a system for managing synonyms that comprises;

a cache line tracker to track cache lines using a directory;

a synonym virtual address bit examiner to examines a bit of a virtual address;

a physical address predictor coupled the cache line tracker and the synonym virtual address bit examiner, the physical address predictor to receive an access request to a VIPT cache that is associated with a first virtual address having a synonym virtual address (VA) bit that is the same as a synonym VA bit of a second virtual address associated with a previously received access request, and to predict a value of a bit of a physical address associated with said first virtual address in advance of determining the actual value of the bit of the physical address;

a prediction accuracy determiner to determine an actual value of the bit of the physical address, and to provide an indication of a miss and update a predictor, in response to the predicted value of the bit of the physical address provided in advance being different from the actual value of the bit of the physical address; and

request retry component to retry the access request using the actual value of the bit of the physical address.

9. The cache memory system of claim 8, wherein the first virtual address and the second virtual address are associated with separate processes.

10. The cache memory system of claim 8, wherein different physical addresses are associated with the first virtual address and the second virtual address.

11. The cache memory system of claim 8, wherein a same physical address is associated with the first virtual address and the second virtual address.

12. The cache memory system of claim 8, wherein the first virtual address is in a first cache line of the VIPT cache and the second virtual address is in a second cache line of the VIPT cache.

13. The cache memory system of claim 12, wherein the first cache line is in a first panel of the VIPT cache and the second cache line is in a second panel of the VIPT cache.

14. The cache memory system of claim 13, wherein a first value of the VA bit is associated with the first panel and a second value of the VA bit is associated with the second panel.

15. A system, comprising:

a processor to execute instructions;

a system interface to access machine resources; and

a cache coupled to the processor, the cache to including,

a memory controller, wherein said memory controller includes a system for managing synonyms, the memory controller including,

a cache line tracker to track cache lines using a directory;

a synonym virtual address bit examiner to examines a bit of a virtual address;

a physical address predictor coupled the cache line tracker and the synonym virtual address bit examiner, the physical address predictor to receive an access request to a VIPT cache that is associated with a first virtual address having a synonym virtual address (VA) bit that is the same as a synonym VA bit of a second virtual address associated with a previously received access request, and to predict a value of a bit of a physical address associated with said first virtual address in advance of determining the actual value of the bit of the physical address;

a prediction accuracy determiner to determine an actual value of the bit of the physical address, and to provide an indication of a miss and update a predictor, in response to the predicted value of the bit of the physical address provided in advance being different from the actual value of the bit of the physical address; and

request retry component to retry the access request using the actual value of the bit of the physical address.

16. The system of claim 15, wherein the first virtual address and the second virtual address are associated with separate processes.

17. The system of claim 15, wherein the first virtual address is in a first cache line of the VIPT cache and the second virtual address is in a second cache line of the VIPT cache.

18. The system of claim 15, wherein the first cache line is in a first panel of the VIPT cache and the second cache line is in a second panel of the VIPT cache.

19. The system of claim 18, wherein a first value of the VA bit is associated with the first panel and a second value of the VA bit is associated with the second panel.