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ASYMMETRIC MEMORY TAG ACCESS AND DESIGN

  • US 20200133862A1
  • Filed: 10/29/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/29/2018
  • Status: Active Grant
First Claim
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1. A method of accessing tag information in a memory line, comprising:

  • determining, by a computing core, an operation to perform on at least one memory line of a memory, the at least one memory line comprising;

    (i) an address portion comprising one or more address bits indicative of an address of an associated cache line, and (ii) a flag portion comprising one or more flag bits indicative of whether the associated cache line is;

    (i) valid or invalid, and (ii) dirty or not dirty, wherein each of the flag portion and the address portion are accessible by the computing core independent of the other via separate instances of hardware; and

    performing the operation by accessing, by the computing core, only the flag portion of the at least one memory line independent of the address portion of the at least one memory line.

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