ASYMMETRIC MEMORY TAG ACCESS AND DESIGN

• US 20200133862A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: RANGARAJAN, Bharat Kumar, JUNG, Chulmin, MISRA, Rakesh
• Granted Patent: US 10,831,667 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/6032 Way prediction in set-associative cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

Claims

1. A method of accessing tag information in a memory line, comprising:

determining, by a computing core, an operation to perform on at least one memory line of a memory, the at least one memory line comprising;

(i) an address portion comprising one or more address bits indicative of an address of an associated cache line, and (ii) a flag portion comprising one or more flag bits indicative of whether the associated cache line is;

(i) valid or invalid, and (ii) dirty or not dirty, wherein each of the flag portion and the address portion are accessible by the computing core independent of the other via separate instances of hardware; and

performing the operation by accessing, by the computing core, only the flag portion of the at least one memory line independent of the address portion of the at least one memory line.

3. The method of claim 1, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid, not accessing the address bits of the at least one memory line.

4. The method of claim 1, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

determining if the flag portion indicates dirty based on a dirty bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid and the dirty bit indicates dirty, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid or the dirty bit indicates not dirty, not accessing the address bits of the at least one memory line.

5. The method of claim 1, wherein the operation comprises an invalidation operation, and wherein accessing only the flag portion of the at least one memory line comprises writing a valid bit of only the flag portion of the at least one memory line to invalid.

6. The method of claim 1, wherein the at least one memory line comprises a plurality of memory lines.

7. The method of claim 1, wherein accessing comprises one of reading or writing.

21. The method of claim 1, wherein the separate instances of hardware include one or more of a via, a switch, or a connector separately dedicated to each of the flag portion and the address portion.

2. (canceled)

8. A computing device, comprising:

at least one computing core; and

a memory associated with the at least one computing core, wherein the memory comprises at least one memory line, wherein the at least one computing core is configured to;

determine an operation to perform on the at least one memory line, the at least one memory line comprising;

(i) an address portion comprising one or more address bits indicative of an address of an associated cache line, and (ii) a flag portion comprising one or more flag bits indicative of whether the associated cache line is;

(i) valid or invalid, and (ii) dirty or not dirty, wherein each of the flag portion and the address portion are accessible by the computing core independent of the other via separate instances of hardware; and

perform the operation by accessing only the flag portion of the at least one memory line independent of the address portion of the at least one memory line.

10. The computing device of claim 8, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid, not accessing the address bits of the at least one memory line.

11. The computing device of claim 8, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

determining if the flag portion indicates dirty based on a dirty bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid and the dirty bit indicates dirty, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid or the dirty bit indicates not dirty, not accessing the address bits of the at least one memory line.

12. The computing device of claim 8, wherein the operation comprises an invalidation operation, and wherein accessing only the flag portion of the at least one memory line comprises writing a valid bit of only the flag portion of the at least one memory line to invalid.

13. The computing device of claim 8, wherein the at least one memory line comprises a plurality of memory lines.

14. The computing device of claim 8, wherein accessing comprises one of reading or writing.

9. (canceled)

15. A non-transitory computer readable medium that includes instructions that when executed by a computing core causes the computing core to perform a method of accessing tag information in a memory line, the method comprising:

determining an operation to perform on at least one memory line of a memory, the at least one memory line comprising;

(i) an address portion comprising one or more address bits of an associated cache line, and (ii) a flag portion comprising one or more flag bits indicative of whether the associated cache line is;

(i) valid or invalid, and (ii) dirty or not dirty, wherein each of the flag portion and the address portion are accessible by the computing core independent of the other via separate instances of hardware; and

performing the operation by accessing only the flag portion of the at least one memory line independent of the address portion of the at least one memory line.

17. The non-transitory computer readable medium of claim 15, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid, not accessing the address bits of the at least one memory line.

18. The non-transitory computer readable medium of claim 15, wherein the operation comprises a flush operation, wherein accessing only the flag portion of the at least one memory line comprises reading only the flag portion of the at least one memory line, and wherein performing the operation comprises:

determining if the flag portion indicates valid based on a valid bit of the one or more flag bits of the at least one memory line;

determining if the flag portion indicates dirty based on a dirty bit of the one or more flag bits of the at least one memory line;

when the valid bit indicates valid and the dirty bit indicates dirty, flushing a cache line indicated by the address bits of the at least one memory line to a second memory; and

when the valid bit indicates invalid or the dirty bit indicates not dirty, not accessing the remaining bits of the at least one memory line.

19. The non-transitory computer readable medium of claim 15, wherein the operation comprises an invalidation operation, and wherein accessing only the flag portion of the at least one memory line comprises writing a valid bit of only the flag portion of the at least one memory line to invalid.

20. The non-transitory computer readable medium of claim 15, wherein the at least one memory line comprises a plurality of memory lines.

16. (canceled)