SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A LOAD-RESERVE INSTRUCTION

• US 20200133873A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: WILLIAMS, DEREK E., GUTHRIE, GUY L.
• Granted Patent: US 11,068,407 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0853 Cache with multiport tag or data arrays
• CPC Class Codes: G06F 12/0857 by multiple requestors
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a load-type instruction. Execution of the load-type instruction generates a corresponding request that specifies a target address. The processing unit further includes a read-claim state machine that, responsive to receipt of the request, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the request.

Claims

1. A processing unit for a data processing system including multiple processing units all having access to a shared memory via a system interconnect, said processing unit comprising:

a processor core that executes memory access instructions including a load-type instruction, wherein execution of the load-type instruction generates a corresponding core request that specifies a target address; and

a cache memory coupled to the processor core, wherein the cache memory includes a directory and is configured to perform;

responsive to receipt of the core request, determining whether the target address hits in the directory;

based on determining the target address hits in the directory, refraining from issuing on the system interconnect an memory access request for data identified by the target address, servicing the core request, and protecting the target address against access by a conflicting memory access request during a protection interval following servicing of the core request.

2. The processing unit of claim 1, wherein:

the load-type instruction is executed by a given hardware thread;

the core request is a prior core request; and

the cache memory, responsive to receipt from the processor core of a subsequent core request of the given hardware thread that specifies the target address, ends the protection interval.

3. The processing unit of claim 2, wherein the subsequent core request is a load-reserve request.

4. The processing unit of claim 2, wherein the subsequent core request is a store-conditional request.

5. The processing unit of claim 2, wherein:

the cache memory includes a plurality of read-claim state machines including a read-claim state machine allocated by the cache memory to service the core request; and

the read-claim state machine remains in a busy state following servicing of the prior core request and services the subsequent core request.

6. The processing unit of claim 1, and further comprising a timer that determines a maximum duration of the protection interval.

7. The processing unit of claim 1, wherein the cache memory terminates the protection interval in response to execution by the processor core of an instruction explicitly terminating the protection interval.

8. A data processing system, comprising:

the multiple processing units, including the processing unit of claim 1;

the shared memory; and

the system interconnect communicatively coupling the shared memory and the multiple processing units.

9. A method of data processing in a processing unit of a data processing system including multiple processing units all having access to a shared memory via a system interconnect, the processing unit including a processor core and a cache memory, said method comprising:

a processor core executing memory access instructions including a load-type instruction, wherein execution of the load-type instruction generates a corresponding core request that specifies a target address; and

the cache memory, responsive to receipt of the core request;

determining whether the target address hits in the directory;

based on determining the target address hits in the directory, refraining from issuing on the system interconnect an memory access request for data identified by the target address, servicing the core request, and protecting the target address against access by a conflicting memory access request during a protection interval following servicing of the core request.

10. The method of claim 9, wherein:

the load-type instruction is executed by a given hardware thread;

the request is a prior core request; and

the method further comprises the cache memory, responsive to receipt from the processor core of a subsequent core request of the given hardware thread that specifies the target address, ending the protection interval.

11. The method of claim 10, wherein the subsequent core request is a load-reserve request.

12. The method of claim 10, wherein the subsequent core request is a store-conditional request.

13. The method of claim 10, wherein:

the cache memory includes a plurality of read-claim state machines including a read-claim state machine allocated by the cache memory to service the core request; and

the method further comprises the read-claim state machine remaining in a busy state following servicing of the prior core request and servicing the subsequent core request.

14. The method of claim 9, and further comprising determining a maximum duration of the protection interval by reference to a timer.

15. The method of claim 9, and further comprising the cache memory terminating the protection interval in response to execution by the processor core of an instruction explicitly terminating the protection interval.

16. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a data processing system including multiple processing units all having access to a shared memory via a system interconnect, said processing unit including;

a processor core that executes memory access instructions including a load-type instruction, wherein execution of the load-type instruction generates a corresponding core request that specifies a target address; and

a cache memory coupled to the processor core, wherein the cache memory includes a directory and is configured to perform;

responsive to receipt of the core request, determining whether the target address hits in the directory;

based on determining the target address hits in the directory, refraining from issuing on the system interconnect an memory access request for data identified by the target address, servicing the core request, and protecting the target address against access by a conflicting memory access request during a protection interval following servicing of the core request.

17. The design structure of claim 16, wherein:

the load-type instruction is executed by a given hardware thread;

the request is a prior core request; and

the read-claim state machine, responsive to receipt from the processor core of a subsequent core request of the given hardware thread that specifies the target address, ends the protection interval.

18. The design structure of claim 17, wherein the subsequent core request is a load-reserve request.

19. The design structure of claim 17, wherein the subsequent core request is a store-conditional request.

20. The design structure of claim 17, wherein:

the cache memory includes a plurality of read-claim state machines including a read-claim state machine allocated by the cache memory to service the core request; and

the read-claim state machine remains in a busy state following servicing of the prior core request and services the subsequent core request.