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MANAGED NVM ADAPTIVE CACHE MANAGEMENT

  • US 20200133874A1
  • Filed: 12/31/2019
  • Published: 04/30/2020
  • Est. Priority Date: 08/30/2017
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache;

    a memory controller operable to execute instructions which when executed cause the memory controller to perform operations comprising;

    receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to the array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device;

    responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and

    receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache.

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