MANAGED NVM ADAPTIVE CACHE MANAGEMENT
First Claim
1. A memory device, comprising:
- an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache;
a memory controller operable to execute instructions which when executed cause the memory controller to perform operations comprising;
receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to the array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device;
responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and
receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache.
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Accused Products
Abstract
Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.
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Citations
20 Claims
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1. A memory device, comprising:
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an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache; a memory controller operable to execute instructions which when executed cause the memory controller to perform operations comprising; receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to the array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device; responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method performed by a memory controller, the method comprising:
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receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to an array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache; responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A machine-readable medium, storing instructions, which when executed by a memory controller, cause the memory controller to perform operations comprising:
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receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to an array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache; responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification