MANAGED NVM ADAPTIVE CACHE MANAGEMENT

• US 20200133874A1
• Filed: 12/31/2019
• Published: 04/30/2020
• Est. Priority Date: 08/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Christensen, Carla L., Huang, Jianmin, Jean, Sebastien Andre, Tanpairoj, Kulachet
• Granted Patent: US 11,403,013 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Claims

1. A memory device, comprising:

an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache;

a memory controller operable to execute instructions which when executed cause the memory controller to perform operations comprising;

receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to the array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device;

responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and

receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache.

2. The memory device of claim 1, wherein the message is received from the host over an interface according to a Universal Flash Storage (UFS) specification.

3. The memory device of claim 1, wherein the size of the first set is further determined based upon an expected size of the data indicated by the message and in response to a number of available MLC cells.

4. The memory device of claim 1, wherein the array of memory cells are NAND memory cells.

5. The memory device of claim 1, wherein the message from the host indicating that the host is preparing to request that the memory device write an amount of data that exceeds the specified threshold is provided by an operating system executing on the host.

6. The memory device of claim 1, wherein the operations further comprise receiving a sleep or hibernate indication, and in response, executing an SLC cache routine to begin garbage collection of the enlarged SLC cache.

7. The memory device of claim 1, wherein the operations further comprise receiving a low power indication, and in response, bypassing the SLC cache when servicing a subsequent write request.

8. A method performed by a memory controller, the method comprising:

receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to an array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache;

responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and

receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache.

9. The method of claim 8, wherein the message is received from the host over an interface according to a Universal Flash Storage (UFS) specification.

10. The method of claim 8, wherein the size of the first set is further determined based upon an expected size of the data indicated by the message and in response to a number of available MLC cells.

11. The method of claim 8, wherein the array of memory cells are NAND memory cells.

12. The method of claim 8, wherein the message from the host indicating that the host is preparing to request that the memory device write an amount of data that exceeds the specified threshold is provided by an operating system executing on the host.

13. The method of claim 8, wherein the method further comprises receiving a sleep or hibernate indication, and in response, executing an SLC cache routine to begin garbage collection of the enlarged SLC cache.

14. The method of claim 8, wherein the method further comprises receiving a low power indication, and in response, bypassing the SLC cache when servicing a subsequent write request.

15. A machine-readable medium, storing instructions, which when executed by a memory controller, cause the memory controller to perform operations comprising:

receiving a message from a host indicating that the host will write an amount of data that exceeds a specified threshold in a specified period of time to an array of memory cells, the message received by the memory device prior to a receipt of data indicated by the message by the memory device, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, a group of memory cells in the array that are configured as SLC comprising an SLC cache;

responsive to receiving the message, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC and adding the reconfigured first set to the SLC cache to establish an enlarged SLC cache, a size of the first set determined in response to an expected size of the amount of data; and

receiving data corresponding to the message and writing at least a portion of the data to the enlarged SLC cache.

16. The machine-readable medium of claim 15, wherein the message is received from the host over an interface according to a Universal Flash Storage (UFS) specification.

17. The machine-readable medium of claim 15, wherein the size of the first set is further determined based upon an expected size of the data indicated by the message and in response to a number of available MLC cells.

18. The machine-readable medium of claim 15, wherein the array of memory cells are NAND memory cells.

19. The machine-readable medium of claim 15, wherein the message from the host indicating that the host is preparing to request that the memory device write an amount of data that exceeds the specified threshold is provided by an operating system executing on the host.

20. The machine-readable medium of claim 15, wherein the operations further comprise receiving a sleep or hibernate indication, and in response, executing an SLC cache routine to begin garbage collection of the enlarged SLC cache.