MAPPING ENTRY INVALIDATION

• US 20200133877A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Walker, Shawn K., Kroeger, Christopher Shawn
• Granted Patent: US 11,249,918 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/651 Multi-level translation tables
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

Claims

1. A memory access system comprising:

a first memory address translator to translate a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol, the first memory address translator to track memory access request completions;

a second memory address translator to translate the second virtual address to a physical address of a memory;

a mapping entry invalidator to request invalidation of a first mapping entry of the first mapping address translator and to request invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

2. The memory access system of claim 1, wherein the first memory address translator stores a first value for a counter based upon a snapshot of outstanding uncompleted memory access requests transmitted to the second memory access translator upon invalidation of the first mapping entry, wherein the first memory address translator stores a second value, different than the first value, for the counter in response to completion of all previously outstanding uncompleted memory access requests and wherein the mapping entry invalidator is to transmit at least two counter read requests to the first memory address translator following invalidation of the first mapping entry, and wherein the mapping entry invalidator is to request invalidation of the second mapping entry of the second memory address translator based upon a comparison values for the counter received in response to the at least two counter read requests.

3. The memory access system of claim 2 further comprising a second mapping entry invalidator, wherein the second mapping entry invalidator is to transmit at least two counter read requests to the first memory address translator following invalidation of the first mapping entry, wherein the mapping entry invalidator is to request invalidation of the second mapping entry of the second memory address translator based upon a comparison values for the counter received in response to the at least two counter read requests.

4. The memory access system of claim 3, wherein the first mapping entry invalidator is to request invalidation of the second mapping entry of the second memory address translator in response to multiple changes in values for the counter, wherein the second mapping entry invalidator is to request invalidation of the second mapping entry of the second memory address translator in response to multiple changes in values for the counter.

5. The memory access system of claim 1, wherein the second protocol is a Peripheral Component Interconnect Express (PCIe) protocol.

6. The memory access system of claim 1, wherein the second memory address translator is an input output memory management unit (IOMMU).

7. The memory access system of claim 1, wherein the mapping entry invalidator is part of a central processing unit core of a computing system.

8. A memory address translator comprising:

a mapping table having entries linking a first virtual address;

in a first protocol to a second address;

a tracker to track outstanding uncompleted memory access requests output by the memory address translator;

a snapshot module to capture a snapshot of outstanding uncompleted memory access requests corresponding to a mapping entry of the mapping table in response to invalidation of the mapping entry in the mapping table.

9. The memory address translator of claim 8 further comprising a counter, wherein the counter stores a value that changes in response to completion of the outstanding uncompleted memory access requests.

10. The memory address translator of claim 9, wherein the memory address translator is to output the value of the counter in response to receiving a read request from a mapping entry invalidator.

11. A memory entry invalidator comprising a non-transitory computer-readable medium having instructions to direct a processor to:

output a first entry invalidation request to a first memory address translator, the first entry invalidation request requesting invalidation of a mapping entry of a mapping table;

receive an indication from the first memory address translator that all outstanding uncompleted memory access requests, corresponding to the mapping entry of the mapping table and output by the first memory address translator to a second memory address translator prior to invalidation of the mapping entry, have been completed; and

in response to receiving the indication, output a second entry invalidation request to the second memory address translator, the secondary entry invalidation request requesting invalidation of a second mapping entry of a second mapping table of the second memory address translator.

12. The mapping entry invalidator of claim 11, wherein the instructions are to direct the processor to:

output a first read request to the first memory address translator following the output of the first entry invalidation request, the first read request requesting an indication of existence of uncompleted outstanding memory access requests corresponding to the mapping entry of the mapping table of the first memory address translator at the invalidation of the mapping entry of the mapping table;

output a second read request to the first memory address translator, following the first read request, the second request, the second read request requesting an indication of existence of uncompleted outstanding memory access requests corresponding to the mapping entry of the mapping table of the first memory address translator.

13. The mapping entry invalidator of claim 12 further comprising:

receiving a counter value for each of the first read request and the second read request, the counter value being based upon the existence of uncompleted outstanding memory access requests corresponding to the mapping entry of the mapping table of the first memory address translator;

comparing the counter value of the first read request to the counter value of the second read request; and

outputting the second entry invalidation request to the second memory address translator based upon the comparing.

14. The mapping entry invalidator of claim 11, wherein the memory address invalidator is part of a central processing unit core of a computing system.

15. The mapping entry invalidator of claim 11, wherein the first memory address translator operates according to a first protocol and wherein the second memory address translator operates according to a second protocol different than the first protocol

16. The mapping entry invalidator of claim 15, wherein the second protocol comprises a Peripheral Component Interconnect Express (PCIe) protocol.

17. The mapping entry invalidator of claim 11, wherein the second memory address translator is an input output memory management unit (IOMMU) that translates a virtual address to a physical address.