SELECTIVELY ENABLED RESULT LOOKASIDE BUFFER

• US 20200133880A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: ARGADE, Pramod V., PERONI, Daniel Nikolai
• Granted Patent: US 11,675,591 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/34 Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers

Abstract

A processing system selectively enables and disables a result lookaside buffer (RLB) based on a hit rate tracked by a counter, thereby reducing power consumption for lookups at the result lookaside buffer during periods of low hit rates and improving the overall hit rate for the result lookaside buffer. A controller increments the counter in the event of a hit at the RLB and decrements the counter in the event of a miss at the RLB. If the value of the counter falls below a threshold value, the processing system temporarily disables the RLB for a programmable period of time. After the period of time, the processing system re-enables the RLB and resets the counter to an initial value.

Claims

1. A method comprising:

storing, at a tag portion of a buffer, first instruction information comprising a first opcode and a first set of operands, the first set comprising at least one operand;

storing, at a data portion of the buffer, a first result of a first operation performed on the first set of operands based on the first opcode;

in response to receiving an instruction for execution at a computation unit, the instruction comprising a second opcode and a second set of operands, the second set comprising at least one operand, comparing the second opcode and the second set of operands to the first instruction information stored at the tag portion of the buffer;

accessing the first result at the data portion of the buffer in response to the second opcode and the second set of operands matching the first instruction information;

tracking, at a counter, an instance of the second opcode and the second set of operands matching the first instruction information; and

disabling the buffer in response to a value of the counter being less than a threshold value.

2. The method of claim 1, wherein tracking comprises:

incrementing the counter by a first number in response to an instance of the second opcode and the second set of operands matching the first instruction information.

3. The method of claim 2, wherein tracking further comprises:

decrementing the counter by a second number in response to an instance of the second opcode and the second set of operands not matching the first instruction information.

4. The method of claim 3, wherein tracking further comprises setting a maximum value for the counter.

5. The method of claim 1, further comprising:

re-enabling the buffer a first number of clock cycles after disabling the buffer; and

setting the counter to an initial value.

6. The method of claim 1, further comprising:

storing, at the tag portion of the buffer, second instruction information comprising a third opcode and a third set of operands, the third opcode different from the first opcode;

storing, at a data portion of the buffer, a second result of a second operation performed on the third set of operands based on the third opcode;

comparing the second opcode and the second set of operands to the second instruction information stored at the tag portion of the buffer;

accessing the second result at the data portion of the buffer in response to the second opcode and the second set of operands matching the second instruction information; and

tracking, at the counter, an instance of the second opcode and the second set of operands matching the second instruction information.

7. The method of claim 1, wherein comparing comprises comparing the N most significant bits of the first set of operands and the second set of operands, wherein N is an integer number less than the number of bits comprising the first set of operands and the second set of operands.

8. A method, comprising:

disabling, in response to a value of a counter being less than a threshold value, a buffer storing, at a tag portion, first instruction information comprising a first opcode and a first set of operands, the first set comprising at least one operand and storing, at a data portion, a first result of a first operation performed on the first set of operands based on the first opcode;

re-enabling the buffer a first number of clock cycles after disabling the buffer;

setting the counter to an initial value;

tracking, at the counter, instances of an instruction for execution at a computation unit matching the first instruction information stored at the tag portion of the buffer, the instruction comprising a second opcode and a second set of operands, the second set comprising at least one operand; and

accessing the first result at the data portion of the buffer in response to the second opcode and the second set of operands matching the first instruction information.

9. The method of claim 8, wherein tracking comprises:

incrementing the counter by a first number in response to an instance of the second opcode and the second set of operands matching the first instruction information.

10. The method of claim 9, wherein tracking further comprises:

decrementing the counter by a second number in response to an instance of the second opcode and the second set of operands not matching the first instruction information.

11. The method of claim 10, wherein tracking further comprises setting a maximum value for the counter.

12. The method of claim 8, further comprising:

storing, at the tag portion of the buffer, second instruction information comprising a third opcode and a third set of operands, the third opcode different from the first opcode;

storing, at a data portion of the buffer, a second result of a second operation performed on the third set of operands based on the third opcode;

comparing the second opcode and the second set of operands to the second instruction information stored at the tag portion of the buffer;

accessing the second result at the data portion of the buffer in response to the second opcode and the second set of operands matching the second instruction information; and

tracking, at the counter, an instance of the second opcode and the second set of operands matching the second instruction information.

13. The method of claim 8, wherein comparing comprises comparing the N most significant bits of the first set of operands and the second set of operands, wherein N is an integer number less than the number of bits comprising the first set of operands and the second set of operands.

14. A device, comprising:

a computation unit to execute a plurality of instructions, each instruction of the plurality of instructions comprising an opcode and a set of operands, the set comprising at least one operand;

a buffer comprising a tag portion and a data portion, the buffer configured to store at the tag portion first instruction information comprising at least one opcode and at least one set of operands for at least one previously executed instruction, and at the data portion corresponding results of operations performed based on the previously executed instructions;

a comparator to compare instructions of the plurality of instructions to the first instruction information at the tag portion of the buffer;

a counter to track instances of an instruction of the plurality of instructions matching first instruction information at the tag portion of the buffer; and

a controller to disable the buffer in response to the counter being less than a threshold value,

wherein the computation unit is configured to access a corresponding result at the data portion of the buffer in response to the instruction of the plurality of instructions matching the first instruction information.

15. The device of claim 14, wherein the controller is to increment the counter by a first number in response to an instance of the instruction of the plurality of instructions matching the first instruction information.

16. The device of claim 15, wherein the controller is to decrement counter by a second number in response to an instance of the instruction of the plurality of instructions not matching the first instruction information.

17. The device of claim 16, wherein the controller is to set a maximum value for the counter.

18. The device of claim 14, wherein the controller is to re-enable the buffer a first number of clock cycles after disabling the buffer and set the counter to an initial value in response to re-enabling the buffer.

19. The device of claim 14, wherein the comparator is to compare the N most significant bits of the set of operands of an instruction and the at least one set of operands stored at the tag portion of the buffer, wherein N is an integer number less than the number of bits comprising the set of operands of an instruction and the at least one set of operands stored at the tag portion of the buffer.

20. The device of claim 14, wherein the buffer is configured to exclude a set of operands.