METHODS AND SYSTEMS FOR OPTIMIZED TRANSLATION LOOKASIDE BUFFER (TLB) LOOKUPS FOR VARIABLE PAGE SIZES

• US 20200133881A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, David, Hicks, Dwain A.
• Granted Patent: US 10,915,459 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 2212/652 Page size control
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]

Abstract

A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.

Claims

1. A method comprising, by a processing system:

receiving a first virtual address for translation to a physical address;

concurrently determining, based on a first portion of the first virtual address and a second portion of the first virtual address, if a translation lookaside buffer (TLB) data cache stores the physical address associated with the first virtual address, wherein;

the TLB data cache includes a first TLB array and a second TLB array,

the first portion is associated with a first page size and the second portion is associated with a second page size that is different from the first page size, and

using the first portion for performing a lookup in either one of the first TLB array and the second TLB array and using the second portion for performing a lookup in other one of the first TLB array and the second TLB array.

2. The method of claim 1, further comprising:

before receiving the first virtual address, configuring the TLB data cache to include the first TLB array and the second TLB array;

identifying a least significant bit (LSB) of effective address bits extracted from a virtual address, wherein the effective address bits are extracted based on a page size of a larger of the first page size and the second page size; and

defining a rule set for associating the first page size with the first TLB array or the second TLB array and for associating the second page size with the first TLB array or the second TLB array during translation based on a value of the LSB in a received virtual address.

3. The method of claim 2, further comprising determining the value of the LSB in the first virtual address.

4. The method of claim 3, further comprising, before the concurrent determination step, using the rule set for associating the first page size with either the first TLB array or the second TLB array and associating the second page size with the other one of the first TLB array or the second TLB array based on the value of the LSB in the first virtual address.

5. The method of claim 4, further comprising configuring the first TLB array and the second TLB array for using a portion of the first virtual address for performing a lookup based on a size of the associated page.

6. The method of claim 2, wherein the value of the LSB is either 0 or 1.

7. The method of claim 2, wherein the rule set includes one or more of the following rules:

if the value of the LSB is 1, associate the larger of the first page size and the second page size with the first TLB array, and the smaller of the first page size and the second page size with the second TLB array;

if the value of the LSB is 0, associate the larger of the first page size and the second page size with the second TLB array, and the smaller of the first page size and the second page size with the first TLB array;

if the value of the LSB is 1, associate the smaller of the first page size and the second page size with the first TLB array, and the larger of the first page size and the second page size with the second TLB array; and

if the value of the LSB is 0, associate the smaller of the first page size and the second page size with the second TLB array, and the larger of the first page size and the second page size with the first TLB array.

8. The method of claim 1, further comprising, in response to determining that the TLB data cache stores the physical address associated with the first virtual address, using an offset portion of the first virtual address to form the physical address.

9. The method of claim 1, further comprising:

in response to determining that the TLB data cache does not store the physical address associated with the first virtual address, determining if page sizes other than the first page size and the second page size are supported by the processing system; and

if page sizes other than the first page size and the second page size are not supported by the processing system, returning a TLB miss output.

10. The method of claim 9, further comprising, in response to determining that page sizes other than the first page size and the second page size are supported by the processing system, concurrently determining, based on a third portion of the first virtual address and a fourth portion of the first virtual address, determining if the TLB data cache stores the physical address associated with the first virtual address, wherein the third portion is associated with a third page size and the fourth portion is associated with a fourth page size.

11. The method of claim 10, further comprising:

identifying a least significant bit (LSB) of effective address bits extracted from a virtual address, wherein the effective address bits are extracted based on a page size of a larger of the third page size and the fourth page size; and

defining a rule set for associating the third page size with the first TLB array or the second TLB array and for associating the fourth page size with the first TLB array or the second TLB array during translation based on a value of the LSB in a received virtual address.

12. The method of claim 1, wherein the first page size and the second page size are selected from the group comprising:

4 KB, 16 KB, 64 KB, 1 MB, 16 MB, and 1 GB.

13. A computing system comprising:

a translation lookaside buffer (TLB) configured to store an entry that comprises virtual address information and real address information associated with the virtual address information, wherein the TLB comprises a first TLB array and a second TLB array;

a processor; and

a non-transitory computer-readable storage medium comprising program instructions that when executed by the processor cause the processor to;

receive a first virtual address for translation to a physical address,

concurrently determine, based on a first portion of the first virtual address and a second portion of the first virtual address, if the TLB stores the physical address associated with the first virtual address, wherein the first portion is associated with a first page size and the second portion is associated with a second page size that is different from the first page size, and

use the first portion for performing a lookup in either one of the first TLB array and the second TLB array and use the second portion for performing a lookup in other one of the first TLB array and the second TLB array.

14. The computing system of claim 13, further comprising programming instructions that cause the processor to:

before receiving the first virtual address, configure the TLB to include the first TLB array and the second TLB array;

identify a least significant bit (LSB) of effective address bits extracted from a virtual address, wherein the effective address bits are extracted based on a page size of a larger of the first page size and the second page size; and

define a rule set for associating the first page size with the first TLB array or the second TLB array and for associating the second page size with the first TLB array or the second TLB array during translation based on a value of the LSB in a received virtual address.

15. The computing system of claim 14, further comprising programming instructions that cause the processor to determine the value of the LSB in the first virtual address.

16. The computing system of claim 15, further comprising programming instructions that cause the processor to, before the concurrent determination step, using the rule set for associating the first page size with either the first TLB array or the second TLB array and associating the second page size with the other one of the first TLB array or the second TLB array based on the value of the LSB in the first virtual address.

17. The computing system of claim 16, further comprising programming instructions that cause the processor to configure the first TLB array and the second TLB array for using a portion of the first virtual address for performing a lookup based on a size of the associated page.

18. The computing system of claim 14, wherein the rule set includes one or more of the following rules:

if the value of the LSB is 1, associate the larger of the first page size and the second page size with the first TLB array, and the smaller of the first page size and the second page size with the second TLB array;

if the value of the LSB is 0, associate the larger of the first page size and the second page size with the second TLB array, and the smaller of the first page size and the second page size with the first TLB array;

if the value of the LSB is 1, associate the smaller of the first page size and the second page size with the first TLB array, and the larger of the first page size and the second page size with the second TLB array; and

if the value of the LSB is 0, associate the smaller of the first page size and the second page size with the second TLB array, and the larger of the first page size and the second page size with the first TLB array.

19. The computing system of claim 13, further comprising programming instructions that cause the processor to:

in response to determining that the TLB does not store the physical address associated with the first virtual address, determine if page sizes other than the first page size and the second page size are supported by the processing system; and

if page sizes other than the first page size and the second page size are not supported by the processing system, return a TLB miss output.

20. The computing system of claim 19, further comprising programming instructions that cause the processor to in response to determining that page sizes other than the first page size and the second page size are supported by the processing system, concurrently determine, based on a third portion of the first virtual address and a fourth portion of the first virtual address, determining if the TLB stores the physical address associated with the first virtual address, wherein the third portion is associated with a third page size and the fourth portion is associated with a fourth page size.