MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20200133882A1
• Filed: 05/29/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Song, Min-O
• Granted Patent: US 11,003,590 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.

Claims

1. A memory system, comprising:

a memory device suitable for storing host data provided from a host; and

a memory controller suitable for managing and transferring the host data between the host and the memory device,

wherein the memory controller comprises;

a write buffer suitable for temporarily storing the host data to be transferred to the memory device;

a buffer monitoring device suitable for checking a usage amount of the write buffer during a predetermined period;

a buffer usage comparing device suitable for generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and

a first flush device suitable for transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.

2. The memory system of claim 1, further comprising a second flush device suitable for transferring the temporarily stored host data to the memory device when the usage amount of the write buffer is greater than a second threshold value.

3. The memory system of claim 2,

wherein the second flush device includes:

a second program data generating unit suitable for generating a program-unit data by dividing the host data temporarily stored in the write buffer by a size corresponding to the second threshold value; and

a second program data transferring unit suitable for transferring the program-unit data to the memory device, and

wherein the program-unit data has a size suitable for being flushed into the memory device by a single flush operation.

4. The memory system of claim 1,

is wherein the first flush device includes:

a first program data generating unit suitable for generating a program-unit data by combining the temporarily stored host data with dummy data; and

a first program data transferring unit suitable for transferring the program-unit data to the memory device, and

wherein the program-unit data has a size suitable for being flushed into the memory device by a single flush operation.

5. The memory system of claim 4, wherein the size of the program-unit data is a page.

6. The memory system of claim 4, wherein the size of the program-unit data is a mufti-plane page.

7. The memory system of claim 4, wherein the size of the program-unit data is a one-shot program unit.

8. The memory system of claim 1, wherein the memory controller further comprises a volatile memory that includes the write buffer.

9. The memory system of claim 1, wherein the buffer usage comparing device generates the flush control signal when the usage amount comparison result is smaller than a first threshold value.

10. The memory system of claim 1, wherein the buffer monitoring device includes an internal storage device suitable for storing a usage amount of the write buffer for each predetermined period.

11. A method for operating a memory system, the method comprising:

buffering host data provided from a host in a write buffer;

checking a usage amount of the write buffer during a predetermined period;

generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and

performing a first flush operation of transferring the host data temporarily stored in the write buffer to a memory device in response to the flush control signal.

12. The method of claim 11, further comprising performing a second flush operation of transferring the temporarily stored host data to the memory device when the usage amount of the write buffer is greater than a second threshold value.

13. The method of claim 12,

wherein the performing of the second flush operation includes:

generating a program-unit data by dividing the host data temporarily stored in the write buffer by a size corresponding to the second threshold value; and

transferring the program-unit data to the memory device, and

wherein the program-unit data has a size suitable for being flushed into the memory device by a single flush operation.

14. The method of claim 11, wherein the performing of the first flush operation includes:

generating the program unit data by combining dummy data with the temporarily stored host data; and

transferring the program-unit data to the memory device, and

wherein the program-unit data has a size suitable for being flushed into the memory device by a single flush operation.

15. The method of claim 14, wherein the size of the program-unit data is a page.

16. The method of claim 14, wherein the size of the program-unit data is a multi-plane page.

17. The method of claim 14, wherein the size of the program-unit data is a one-shot program unit.

18. The method of claim 11, wherein the flush control signal is generated when the usage amount comparison result is smaller than a first threshold value.

19. The method of claim 11, wherein the checking includes storing the usage amount of the write buffer for each predetermined period.

20. A memory system comprising:

a memory device;

a buffer suitable for buffering external data; and

a controller suitable for controlling the memory device to periodically perform an internal flush operation of flushing the buffered data therein,

wherein the controller further controls the memory device to skip the internal flush operation of a current period when difference among sizes of the buffered data of last two or more periods varies within a threshold.