SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
First Claim
1. A system, comprising:
- a rank of state machine engines (SMEs) configured to be selected via a common chip select signal, wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs; and
a host coupled to the rank of SMEs and configured to transmit a command to the rank of SMEs in a bus cycle, wherein a first SME of the rank of SMEs is configured to execute the command in conjunction with a first address referencing a first location of the common locations in the bus cycle, wherein a second SME of the rank of SMEs is configured to execute the command in conjunction with a second address referencing a second location of the common locations differing from the first location of the common locations in the bus cycle.
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Abstract
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
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Citations
20 Claims
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1. A system, comprising:
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a rank of state machine engines (SMEs) configured to be selected via a common chip select signal, wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs; and a host coupled to the rank of SMEs and configured to transmit a command to the rank of SMEs in a bus cycle, wherein a first SME of the rank of SMEs is configured to execute the command in conjunction with a first address referencing a first location of the common locations in the bus cycle, wherein a second SME of the rank of SMEs is configured to execute the command in conjunction with a second address referencing a second location of the common locations differing from the first location of the common locations in the bus cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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selecting a rank of state machine engines (SMEs) wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs via a common chip select signal; receiving a command at the rank of SMEs in a bus cycle; executing the command via a first SME of the rank of SMEs in conjunction with a first address referencing a first location of the common locations in the bus cycle; and executing the command via a second SME of the rank of SMEs in conjunction with a second address referencing a second location of the common locations differing from the first location of the common locations in the bus cycle. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system, comprising:
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a rank of state machine engines (SMEs), wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs; a direct address storage (DAS) coupled to the rank of SMEs and configured to store and transmit a first address referencing a first location of the common locations to a first SME of the rank of SMEs in a bus cycle; and an indirect address storage (IAS) coupled to the rank of SMEs and configured to store and transmit a second address referencing a second location of the common locations to a second SME of the rank of SMEs in the bus cycle. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification