SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING

• US 20200133893A1
• Filed: 12/24/2019
• Published: 04/30/2020
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bell, Debra, Glendenning, Paul, Brown, David R., Noyes, Harold B
• Granted Patent: US 10,789,182 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 2213/2802 DMA using DMA transfer descriptors

Abstract

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Claims

1. A system, comprising:

a rank of state machine engines (SMEs) configured to be selected via a common chip select signal, wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs; and

a host coupled to the rank of SMEs and configured to transmit a command to the rank of SMEs in a bus cycle, wherein a first SME of the rank of SMEs is configured to execute the command in conjunction with a first address referencing a first location of the common locations in the bus cycle, wherein a second SME of the rank of SMEs is configured to execute the command in conjunction with a second address referencing a second location of the common locations differing from the first location of the common locations in the bus cycle.

2. The system of claim 1, wherein a third SME of the rank of SMEs is configured to ignore the command in conjunction with the second address referencing the second location of the common locations differing from the first location of the common locations in the bus cycle.

3. The system of claim 1, wherein a third SME of the rank of SMEs is configured to execute the command in conjunction with a third address as a dummy address differing from the address referencing the second location of the common locations and differing from the first location of the common locations in the bus cycle.

4. The system of claim 3, comprising an indirect address storage (IAS) coupled to the rank of SMEs and configured to store and transmit the second address to the second SME of the rank of SMEs.

5. The system of claim 4, wherein the IAS is configured to store and transmit the third address to the third SME of the rank of SMEs.

6. The system of claim 1, comprising a direct address storage (DAS) coupled to the rank of SMEs and configured to store and transmit the first address to the first SME of the rank of SMEs.

7. The system of claim 1, wherein the host is configured to select the rank of SMEs via transmission of the common chip select signal.

8. A method, comprising:

selecting a rank of state machine engines (SMEs) wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs via a common chip select signal;

receiving a command at the rank of SMEs in a bus cycle;

executing the command via a first SME of the rank of SMEs in conjunction with a first address referencing a first location of the common locations in the bus cycle; and

executing the command via a second SME of the rank of SMEs in conjunction with a second address referencing a second location of the common locations differing from the first location of the common locations in the bus cycle.

9. The method of claim 8, comprising ignoring the command via a third SME of the rank of SMEs in conjunction with the second address referencing the second location of the common locations differing from the first location of the common locations in the bus cycle.

10. The method of claim 8, comprising executing the command via a third SME of the rank of SMEs in conjunction with a third address as a dummy address differing from the address referencing the second location of the common locations and differing from the first location of the common locations in the bus cycle.

11. The method of claim 10, comprising storing and transmitting the second address to the second SME of the rank of SMEs via an indirect address storage (IAS) coupled to the rank of SMEs.

12. The method of claim 11, comprising storing and transmitting the third address to the third SME of the rank of SMEs via the IAS.

13. The method of claim 8, comprising storing and transmitting the first address to the first SME of the rank of SMEs via a direct address storage (DAS) coupled to the rank of SMEs.

14. The method of claim 8, comprising transmitting a common chip select signal from a host to select the rank of SMEs.

15. A system, comprising:

a rank of state machine engines (SMEs), wherein each state machine engine (SME) of the rank of SMEs is configured to analyze data via a plurality of configurable elements disposed in common locations in each SME of the rank of SMEs;

a direct address storage (DAS) coupled to the rank of SMEs and configured to store and transmit a first address referencing a first location of the common locations to a first SME of the rank of SMEs in a bus cycle; and

an indirect address storage (IAS) coupled to the rank of SMEs and configured to store and transmit a second address referencing a second location of the common locations to a second SME of the rank of SMEs in the bus cycle.

16. The system of claim 15, wherein the first SME of the rank of SMEs is configured receive the first address and execute a command in conjunction with the first address in the bus cycle.

17. The system of claim 16, wherein the second SME of the rank of SMEs is configured receive the second address and execute the command in conjunction with the second address in the bus cycle.

18. The system of claim 17, wherein a third SME of the rank of SMEs is configured to ignore the command in conjunction with the second address referencing the second location of the common locations differing from the first location of the common locations in the bus cycle.

19. The system of claim 17, wherein the IAS is configured to store and transmit a third address referencing a dummy location differing from each of the first location and the second location of the common locations to a third SME of the rank of SMEs in the bus cycle.

20. The system of claim 17, comprising a host coupled to the IAS, wherein the host is configured to initially configure the IAS.