LOAD REDUCED NONVOLATILE MEMORY INTERFACE

• US 20200133899A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: CHUNG, Emily P., HADY, Frank T., VERGIS, George
• Granted Patent: US 11,500,795 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Claims

1. A system, comprising:

a group of nonvolatile memory (NVM) devices;

a storage controller coupled to the group of NVM devices, the storage controller to manage reading and writing to the NVM devices; and

a data buffer coupled between the group of NVM devices and the storage controller on a data bus, the data buffer to re-drive data signals on the data bus, and synchronize data signals to a clock signal.

2. The system of claim 1, wherein the storage controller is to first send a command signal to the group of NVM devices, and next send a control signal to the data buffer, wherein the control signal is to trigger the data buffer to transfer the data signals to the group of NVM devices.

3. The system of claim 1, wherein the NVM devices are to operate in a burst mode, to transfer data over 2N cycles, and the data buffer is to operate to transfer data over N cycles, wherein the storage controller is to issue consecutive commands to the data buffer to cause the data buffer to operate for 2N cycles in response to the consecutive commands.

4. The system of claim 3, wherein the data buffer is to eliminate stall cycles internally to produce 2N cycles of continuous data transfer in response to the consecutive commands.

5. The system of claim 1, wherein the data buffer comprises a host interface to the storage controller and a memory interface to the group of NVM devices, and wherein the data buffer is to apply different configuration settings for the host interface than the memory interface, wherein the different configuration settings include at least a different timing configuration setting.

6. The system of claim 1, wherein the data buffer is to re-drive data signals from the storage controller to the NVM devices, including to synchronize the data signals to a protocol timing of an interface of the NVM devices.

7. The system of claim 1, wherein the data buffer is to re-drive data signals from the NVM devices to the storage controller, including to synchronize the data signals to a protocol timing of a storage controller interface.

8. The system of claim 1, wherein the group of NVM devices comprises a first group and the data buffer comprises a first data buffer, and further comprising a second group of NVM devices and a second data buffer coupled between the second group of NVM devices and the storage controller.

9. The system of claim 8, further comprising a third data buffer, wherein the first and second groups couple to the storage controller in a cascaded manner, with the third data buffer coupled between the storage controller and the first and second data buffers.

10. The system of claim 1, further comprising a command buffer coupled between the group of NVM devices and the storage controller on a command bus, the command buffer to re-drive command signals on the command bus, and synchronize command signals to a clock signal.

11. The system of claim 1, further comprising one or more of:

at least one processor communicatively coupled to the storage controller;

a memory controller communicatively coupled to the storage controller;

a display communicatively coupled to at least one processor;

a battery to power the system;

or

a network interface communicatively coupled to at least one processor.

12. A solid state drive (SSD), comprising:

a storage controller including an interface to couple to a host processor, the storage controller to manage read and write requests from the host processor; and

multiple storage circuits coupled to the storage controller, including

a plurality of nonvolatile memory (NVM) devices; and

a data buffer coupled between the plurality of NVM devices and the storage controller on a data bus, the data buffer to re-drive data signals on the data bus, and synchronize data signals to a clock signal.

13. The SSD of claim 12, wherein the storage controller is to first send a command signal to the group of NVM devices, and next send a control signal to the data buffer, wherein the control signal is to trigger the data buffer to transfer the data signals to the group of NVM devices.

14. The SSD of claim 12, wherein the data buffer is to re-drive data signals from the storage controller to the NVM devices, including to synchronize the data signals to a protocol timing of an interface of the NVM devices.

15. The SSD of claim 12, wherein the data buffer is to re-drive data signals from the NVM devices to the storage controller, including to synchronize the data signals to a protocol timing of a storage controller interface.

16. The SSD of claim 12, wherein the multiple storage circuits are organized in a cascade, wherein first and second data buffers couple, respectively, to first and second pluralities of NVM devices, and a third data buffer couples between the first and second data buffers and the storage controller.

17. The SSD of claim 12, wherein the multiple storage circuits further comprising:

a command buffer coupled between the group of NVM devices and the storage controller on a command bus, the command buffer to re-drive command signals on the command bus, and synchronize command signals to a clock signal.

18. A method for data access, comprising:

receiving a buffer command at a buffer coupled between a group of nonvolatile memory (NVM) devices and a storage controller, the buffer command to be issued after a data access command issued to the group of NVM devices; and

responsive to receiving the buffer command, re-driving data signals on a data bus between the NVM devices and the storage controller, including synchronizing the data signals to a clock signal.

19. The method of claim 18, wherein receiving the buffer command comprises receiving two consecutive commands, and responsive to receiving the two consecutive commands, re-driving two consecutive bursts of data signals as one double-length burst of data signals;

or

alternatively,

wherein re-driving data signals on the data bus comprises re-driving write data signals from the storage controller to the NVM devices;

or alternatively,

wherein re-driving data signals on the data bus comprises re-driving read data signals from the NVM devices to the storage controller.

20. The method of claim 18, further comprising:

training a host interface coupled to the storage controller, to configure settings for the host interface; and

training a memory interface coupled to the NVM devices, to configure settings for the memory interface, wherein training the memory interface comprises writing fixed data patterns to a register on buffer via the host interface.