MIXING RESTARTABLE AND NON-RESTARTABLE REQUESTS WITH PERFORMANCE ENHANCEMENTS

• US 20200133900A1
• Filed: 07/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jutt, Michael G., Sofia, Anthony T.
• Granted Patent: US 10,901,924 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 2213/40 Bus coupling
• CPC Class Codes: G06F 3/0656 Data buffering arrangements

Abstract

A computer-implemented method includes setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. A hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

Claims

1. A computer-implemented method comprising:

setting a respective flag in a first buffer of a hardware accelerator;

maintaining a hardware state of the hardware accelerator in the first buffer, based on the respective flag of the first buffer being set;

receiving a first request directed to the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the first request to the hardware accelerator, wherein the passing the first request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

2. The computer-implemented method of claim 1, wherein a second buffer of the hardware accelerator comprises a respective flag of the second buffer, the first buffer is a current input buffer for the first request, the second buffer is a current output buffer for the first request, and the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the first request.

3. The computer-implemented method of claim 1, wherein:

the first buffer is a current input buffer for the first request;

a second buffer is a current output buffer for the first request;

responsive to executing the first request, the hardware accelerator writes a resulting software state to the current output buffer; and

the computer-implemented method further comprises swapping the current input buffer and the current output buffer at a conclusion of the first request, wherein the first buffer becomes the current output buffer and the second buffer becomes the current input buffer.

4. The computer-implemented method of claim 3, wherein:

the first buffer is a current output buffer for a next request;

the second buffer is the current input buffer for the next request; and

the computer-implemented method further comprises;

receiving a second request as the next request for the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the second request to the hardware accelerator, wherein the passing the second request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

5. The computer-implemented method of claim 3, wherein the first buffer is a current output buffer for a second request, wherein the second buffer is the current input buffer for the second request, and wherein the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the second request.

6. The computer-implemented method of claim 1, wherein a software state of the hardware accelerator is moveable between the first buffer and a second buffer, and wherein the hardware state of the hardware accelerator is fixed in the first buffer.

7. The computer-implemented method of claim 1, wherein the hardware accelerator supports a restartable request.

8. A system comprising:

a memory having computer-readable instructions; and

one or more processors for executing the computer-readable instructions, the computer-readable instructions comprising instructions for;

setting a respective flag in a first buffer of a hardware accelerator;

maintaining a hardware state of the hardware accelerator in the first buffer, based on the respective flag of the first buffer being set;

receiving a first request directed to the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the first request to the hardware accelerator, wherein the passing the first request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

9. The system of claim 8, wherein a second buffer of the hardware accelerator comprises a respective flag of the second buffer, the first buffer is a current input buffer for the first request, the second buffer is a current output buffer for the first request, and the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the first request.

10. The system of claim 8, wherein:

the first buffer is a current input buffer for the first request;

a second buffer is a current output buffer for the first request;

responsive to executing the first request, the hardware accelerator writes a resulting software state to the current output buffer; and

the computer-readable instructions further comprise instructions for swapping the current input buffer and the current output buffer at a conclusion of the first request, wherein the first buffer becomes the current output buffer and the second buffer becomes the current input buffer.

11. The system of claim 10, wherein:

the first buffer is a current output buffer for a next request;

the second buffer is the current input buffer for the next request; and

the computer-readable instructions further comprise instructions for;

receiving a second request as the next request for the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the second request to the hardware accelerator, wherein the passing the second request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

12. The system of claim 10, wherein the first buffer is a current output buffer for a second request, wherein the second buffer is the current input buffer for the second request, and wherein the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the second request.

13. The system of claim 8, wherein a software state of the hardware accelerator is moveable between the first buffer and a second buffer, and wherein the hardware state of the hardware accelerator is fixed in the first buffer.

14. The system of claim 8, wherein the hardware accelerator supports a restartable request.

15. A computer-program product for executing requests on a hardware accelerator, the computer-program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

setting a respective flag in a first buffer of a hardware accelerator;

maintaining a hardware state of the hardware accelerator in the first buffer, based on the respective flag of the first buffer being set;

receiving a first request directed to the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the first request to the hardware accelerator, wherein the passing the first request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

16. The computer-program product of claim 15, wherein a second buffer of the hardware accelerator comprises a respective flag of the second buffer, first buffer is a current input buffer for the first request, the second buffer is a current output buffer for the first request, and the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the first request.

17. The computer-program product of claim 15, wherein:

the first buffer is a current input buffer for the first request;

a second buffer is a current output buffer for the first request;

responsive to executing the first request, the hardware accelerator writes a resulting software state to the current output buffer; and

the method further comprises swapping the current input buffer and the current output buffer at a conclusion of the first request, wherein the first buffer becomes the current output buffer and the second buffer becomes the current input buffer.

18. The computer-program product of claim 17, wherein:

the first buffer is a current output buffer for a next request;

the second buffer is the current input buffer for the next request; and

the method further comprises;

receiving a second request as the next request for the hardware accelerator;

determining that the first buffer has the respective flag set; and

passing the second request to the hardware accelerator, wherein the passing the second request comprises passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

19. The computer-program product of claim 17, wherein the first buffer is a current output buffer for a second request, wherein the second buffer is the current input buffer for the second request, and wherein the hardware accelerator writes a resulting software state to the current input buffer responsive to executing the second request.

20. The computer-program product of claim 15, wherein a software state of the hardware accelerator is moveable between the first buffer and a second buffer, and wherein the hardware state of the hardware accelerator is fixed in the first buffer.