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SYSTEMS AND METHODS FOR COMBINING MULTIPLE MEMORY CHANNELS

  • US 20200133903A1
  • Filed: 10/24/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/24/2018
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first memory controller configured to access a first channel using a first protocol;

    a second memory controller configured to access a second channel using a second protocol that is different from the first protocol; and

    a physical interface coupled to the first memory controller and a second memory controller, the physical interface comprising;

    a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.

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