SYSTEMS AND METHODS FOR COMBINING MULTIPLE MEMORY CHANNELS

• US 20200133903A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: InnoGrit Technologies Co., Ltd.
• Original Assignee: Nyquist Semiconductor Limited
• Inventors: Chen, Shawn, Jiang, Wei, Chen, Lin
• Granted Patent: US 11,048,654 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, apparatus and methods are provided to combine multiple channels in a multi-channel memory controller to save area and reduce power and cost. An apparatus may comprise a first memory controller configured to access a first channel using a first protocol, a second memory controller configured to access a second channel using a second protocol that is different from the first protocol and a physical interface coupled to the first memory controller and a second memory controller. The physical interface may comprise a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.

Claims

1. An apparatus, comprising:

a first memory controller configured to access a first channel using a first protocol;

a second memory controller configured to access a second channel using a second protocol that is different from the first protocol; and

a physical interface coupled to the first memory controller and a second memory controller, the physical interface comprising;

a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.

2. The apparatus of claim 1, wherein the first protocol and the second protocol are compatible protocols.

3. The apparatus of claim 1, wherein the physical interface comprise at least a first address input coupled to the first memory controller and a second address input coupled to the second memory controller, and the first address input and second address input are mapped to one shared pin of the set of pins.

4. The apparatus of claim 2, wherein the first address input and second address input are configured to work in different time slots.

5. The apparatus of claim 1, wherein the time division multiplexing is achieved by allocating designated different clock cycles to different channels.

6. The apparatus of claim 1, wherein the time division multiplexing is performed using a chip select signal transmitted via one of the set of pins for the address and command bus.

7. The apparatus of claim 1, wherein the first memory controller is operating an address bus at a first frequency and the second memory controller is operating an address bus at a second frequency that is different from the first frequency.

8. The apparatus of claim 7, wherein the physical interface is operating at a highest frequency of the first frequency and second frequency.

9. The apparatus of claim 7, wherein the physical interface further comprises a first clock pin for the first channel and a second clock pin for the second channel.

10. The apparatus of claim 1, wherein the physical interface further comprises separate sets of pins for data buses for the first channel and second channel respectively.

11. A method, comprising:

receiving a first command from a first channel controller of a multi-channel memory controller at a physical interface of the multi-channel memory controller;

receiving a second command from a second channel controller of the multi-channel memory controller at the physical interface, wherein the first command is a command of a first protocol and the second command is a command of a second protocol, and the first memory protocol is different from the second memory protocol;

sending the first command during a first time slot from the physical interface via a set of pins to a first memory module of a first memory type; and

sending the second command during a second time slot from the physical interface via the set of pins to a second memory module of a second memory type, the set of pins shared by the first channel and second channel.

12. The method of claim 11, wherein the first protocol and the second protocol are compatible protocols.

13. The method of claim 11, further comprising mapping a first address input of the physical interface and a second address input of the physical interface to one shared pin of the set of pins, wherein the first address input and second address input are configured to work in different time slots.

14. The method of claim 11, wherein the first time slot and second time slot are different clock cycles assigned to different channels.

15. The method of claim 11, further comprising transmitting a chip select signal via the set of pins to indicate which of the first memory module and second memory module is a target of a command being sent.

16. The method of claim 11, further comprising operating an address bus of the first channel controller at a first frequency and an address bus of the second memory controller at a second frequency that is different from the first frequency, wherein the physical interface is operating at a highest frequency of the first frequency and second frequency.

17. A non-transitory machine-readable medium having information, wherein the information, when read by a hardware processor system, causes the hardware processor system to perform:

receiving a first command from a first channel controller of a multi-channel memory controller at a physical interface of the multi-channel memory controller;

receiving a second command from a second channel controller of the multi-channel memory controller at the physical interface, wherein the first command is a command of a first protocol and the second command is a command of a second protocol, and the first memory protocol is different from the second memory protocol;

sending the first command during a first time slot from the physical interface via a set of pins to a first memory module of a first memory type; and

sending the second command during a second time slot from the physical interface via the set of pins to a second memory module of a second memory type, the set of pins shared by the first channel and second channel.

18. The non-transitory machine-readable medium of claim 17, wherein the information, when read by the hardware processor system, further causes the hardware processor system to perform:

mapping a first address input of the physical interface and a second address input of the physical interface to one shared pin of the set of pins, wherein the first address input and second address input are configured to work in different time slots.

19. The non-transitory machine-readable medium of claim 17, wherein the information, when read by the hardware processor system, further causes the hardware processor system to perform:

transmitting a chip select signal via the set of pins to indicate which of the first memory module and second memory module is a target of a command being sent.

20. The non-transitory machine-readable medium of claim 17, wherein the information, when read by the hardware processor system, further causes the hardware processor system to perform:

operating an address bus of the first channel controller at a first frequency and an address bus of the second memory controller at a second frequency that is different from the first frequency, wherein the physical interface is operating at a highest frequency of the first frequency and second frequency.