INTERPOSER SYSTEMS FOR INFORMATION HANDLING SYSTEMS

• US 20200133907A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Stuewe, John R., Carver, Walt R., Rousset, Stephen P., Haunsperger, Douglas Simon
• Granted Patent: US 10,747,702 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

Claims

1. A computing apparatus, comprising:

a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s), the first CPU socket including a first inter-socket link connector;

a CPU coupled to the first CPU socket;

a base interposer coupled to the additional CPU socket(s), the base interposer including a second inter-socket link and a high-speed input/output signal connector, the second inter-socket link of the base interposer connected to the high-speed input/output signal connector of the same base interposer; and

one or more devices connected to the base interposer,

wherein the second inter-socket link of the base interposer provides a connection to both i) the first inter-socket link connector of the first CPU socket and ii) the high-speed input/output signal connector of the base interposer such that the first inter-socket link connector of the first CPU socket is additionally connected to the high-speed input/output signal connector of the base interposer via the second inter-socket link of the baser interposer,

wherein the base interposer provides a connection between the CPU and the one or more devices.

2. The computing apparatus of claim 1, wherein the one or more devices include input/output devices and the base interposer provides the connection between the CPU and the input/output devices.

3. The computing apparatus of claim 2, wherein the connection between the CPU and the input/output devices includes a connection between the CPU and input/output signal traces of the base interposer.

4. The computing apparatus of claim 1, wherein the one or more devices include memory modules or devices using memory module sockets and the base interposer provides the connection between the CPU and the memory modules or sockets.

5. The computing apparatus of claim 4, wherein the connection between the CPU and the memory modules includes a connection between the CPU and memory signal traces of the base interposer.

6. The computing apparatus of claim 1, further comprising:

a top interposer coupled to the base interposer,

wherein the base interposer provides a connection between the CPU and the top interposer, and the top interposer provides a connection between the base interposer and the one or more devices.

7. The computing apparatus of claim 6, wherein the one or more devices include input/output cable connectors and the top interposer provides the connection between the CPU and the input/output cable connectors.

8. The computing apparatus of claim 6, wherein the one or more devices include storage devices, and the top interposer provides the connection between the CPU and the storage devices.

9. The computing apparatus of claim 6, where the one or more devices include a field-programmable gate array (FPGA) devices, and the top interposer provides the connection between the CPU and the FPGA devices.

10. The computing apparatus of claim 6, wherein the one or more devices includes a peripheral component interconnect express (PCIe) devices, and the top interposer provides the connection between the CPU and the PCIe devices.

11. The computing apparatus of claim 6, wherein the top interposer further includes a signal integrity boost device.

12. A computing apparatus, comprising:

a printed circuit board (PCB) including a first central processing unit (CPU) socket additional CPU socket(s), the first CPU socket including a first inter-socket link connector;

a CPU coupled to the first CPU socket; and

an interposer stack including;

a base interposer coupled to the additional CPU socket(s), the base interposer including a second inter-socket link and a high-speed input/output signal connector, the second inter-socket link of the base interposer connected to the high-speed input/output signal connector of the same base interposer;

a top interposer coupled to the base interposer, wherein a retention mechanism physically couples the top interposer to the PCB,

wherein the second inter-socket link of the base interposer provides a connection to both i) the first inter-socket link connector of the first CPU socket and ii) the high-speed input/output signal connector of the base interposer such that the first inter-socket link connector of the first CPU socket is additionally connected to the high-speed input/output signal connector of the base interposer via the second inter-socket link of the base interposer.

13. The computing apparatus of claim 12, wherein the retention mechanism includes a bracket coupled to the top interposer, the bracket physically coupling the top interposer to the PCB.

14. The computing apparatus of claim 13, further comprising a plurality of memory sockets, wherein the bracket physically couples the top interposer to the memory sockets.

15. The computing apparatus of claim 12, further comprising a plurality of heat sink mounting pins, wherein the top interposer is physically coupled to the heat sink mounting pins.

16. The computing apparatus of claim 15, wherein the heat sink mounting pins align the top interposer with the base interposer.

17. The computing apparatus of claim 12, further comprising one or more devices connected to the top interposer, wherein the top interposer provides a connection between the CPU and the one or more devices.