WRITES TO MULTIPLE MEMORY DESTINATIONS

• US 20200133909A1
• Filed: 12/24/2019
• Published: 04/30/2020
• Est. Priority Date: 03/04/2019
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: HEFTY, Mark Sean, DAVIS, Arlin R.
• Application Number:
  US16/726,676
• Publication Number:
  US 20200133909A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/6227 where protection concerns the structure of data, e.g. records, types, queries
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 45/566 Routing instructions carried by the data packet, e.g. active networks
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/321 Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers

Abstract

Examples described herein relate to configuring a target network interface to recognize packets that are to be written directly from the network interface to multiple memory destinations. A packet can include an identifier that a portion of the packet is to be written to multiple memory devices at specific addresses. The packet is validated to determine if the target network interface is permitted to directly copy the portion of the packet to memory of the target. The target network interface can perform a direct copy to multiple memory locations of a portion of the packet.

Claims

1. An apparatus comprising:

a memory and

a network interface comprising at least one processor communicatively coupled to the memory, the at least one processor to;

access a packet and

based on the packet including a designation to copy a portion of the packet to at least two destinations in the memory;

copy a first portion of the packet to a first destination based on the designation and

copy the first portion of the packet to a second destination based on the designation.

2. The apparatus of claim 1, wherein the at least one processor is to:

determine if the packet includes a designation to copy a portion of the packet to at least two destinations in the memory.

3. The apparatus of claim 1, wherein:

the packet includes the first portion and a second portion and

based on the packet including a designation to copy the first portion to an associated at least one destination and the second portion to an associated at least one destination, the network interface is to perform at least one copy of the first portion to the associated at least one destination and the network interface is to perform at least one copy of the second portion to the associated at least one destination.

4. The apparatus of claim 3, wherein the first portion is different than the second portion.

5. The apparatus of claim 1, wherein:

the packet includes the first portion, a second portion and a third portion and

based on the packet including a designation to copy the first portion to an associated at least one destination, the second portion to an associated at least one destination, and the third portion to an associated at least one destination, the network interface is to;

perform at least one copy of the first portion to the associated at least one destination,

perform at least one copy of the second portion to the associated at least one destination, and

perform at least one copy of the third portion to the associated at least one destination.

6. The apparatus of claim 1, wherein the designation comprises a portion of a header that indicates performance of a multi-write operation and at least one destination.

7. The apparatus of claim 1, wherein the designation comprises a header that indicates one or more of:

an op code to specify a multi-write operation, a number of memory regions that the portion will be written to, a size of incoming payload, or an offset into a memory region where a write is to begin.

8. The apparatus of claim 1, comprising at least one direct memory access (DMA) engine to perform a copy of the first portion of the packet to the first destination and the second destination.

9. The apparatus of claim 1, wherein the first destination and the second destination comprise memory addresses accessible to one or more of:

an accelerator, graphics processing unit, or central processing unit.

10. The apparatus of claim 1 further comprising one or more of:

a compute sled, a data center, server, rack, blade, or a host computer.

11. A method comprising:

receiving a single packet with an indication to copy a portion of the packet to a first destination and to copy a second portion of the packet to a second destination;

performing, by a direct memory access, a copy of the portion to the first destination; and

performing, by a direct memory access, a copy of the second portion to the second destination.

12. The method of claim 11, wherein a network interface performs the receiving and performing the copies.

13. The method of claim 11, wherein the portion immediately precedes the second portion in the single packet.

14. The method of claim 11, wherein the single packet includes an indication to copy a third portion of the packet to a third destination and to copy a fourth portion of the packet to a fourth destination and comprising:

performing, by a direct memory access operation, a copy of the third portion to the third destination and

performing, by a direct memory access operation, a copy of the fourth portion to the fourth destination.

15. The method of claim 11, wherein the indication comprises a portion of a header of the packet that indicates performance of a multi-write operation and at least one destination.

16. The method of claim 11, wherein the indication comprises a header that indicates one or more of:

an op code to specify a multi-write operation, a number of memory regions that a portion will be written to, a size of incoming payload, or an offset into a memory region where the write is to begin.

17. The method of claim 11, comprising processing data in the first and second destinations using one or more of:

an accelerator, graphics processing unit, or central processing unit.

18. A computer-readable medium comprising instructions stored thereon, that if executed, causes at least one processor to perform:

request a packet to be formed with a header that includes an indication to copy content of the packet to multiple destinations and

cause a single copy of the packet to be transmitted to a destination.

19. The computer-readable medium of claim 18, wherein the indication comprises a portion of a header of the packet that indicates performance of a multi-write operation and at least one destination.

20. The computer-readable medium of claim 18, wherein the indication comprises a header that indicates one or more of:

an op code to specify a multi-write operation, a number of memory regions that content will be written to, a size of incoming payload, or an offset into a memory region where the write is to begin.

21. The computer-readable medium of claim 18, comprising instructions stored thereon, that if executed, cause at least one processor to perform:

configure a network interface to establish and use a remote direct memory access (RDMA) to cause a copy of content of the packet to multiple destinations in memory.