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WRITES TO MULTIPLE MEMORY DESTINATIONS

  • US 20200133909A1
  • Filed: 12/24/2019
  • Published: 04/30/2020
  • Est. Priority Date: 03/04/2019
  • Status: Active Application
First Claim
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1. An apparatus comprising:

  • a memory anda network interface comprising at least one processor communicatively coupled to the memory, the at least one processor to;

    access a packet andbased on the packet including a designation to copy a portion of the packet to at least two destinations in the memory;

    copy a first portion of the packet to a first destination based on the designation andcopy the first portion of the packet to a second destination based on the designation.

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