NEURAL NETWORK PROCESSOR AND CONVOLUTION OPERATION METHOD THEREOF

• US 20200133989A1
• Filed: 07/29/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SONG, Jin-ook, JO, Jihyuck
• Granted Patent: US 11,244,028 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 2207/4824 Neural networks
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/461 Adding; subtracting
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/08 Learning methods

Abstract

A neural network processor for performing a neural network operation may include a memory storing computer-readable instructions, and kernel intermediate data, the kernel intermediate data including a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and at least one processor to execute the computer-readable instructions to perform a convolution operation by selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on an input feature map.

Claims

1. A neural network processor for performing a neural network operation, the neural network processor comprising:

a memory storing computer-readable instructions, and kernel intermediate data, the kernel intermediate data comprising a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and

at least one processor configured to execute the computer-readable instructions to perform a convolution operation by selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on an input feature map.

2. The neural network processor of claim 1, wherein each of the plurality of kernel intermediate values is a value obtained through a linear combination of the plurality of weight values, and each of a plurality of coefficients used in the linear combination has a value of ‘

0’

or ‘

1’

.

3. The neural network processor of claim 1, wherein each of the plurality of kernel intermediate values is a value obtained through a linear combination of the plurality of weight values, and each of a plurality of coefficients used in the linear combination has a value of ‘

−

1’

or ‘

1’

.

4. The neural network processor of claim 3, wherein the plurality of kernel intermediate values comprises 2̂

(N−

1) kernel intermediate values, N being a natural number.

5. The neural network processor of claim 1, wherein the at least one processor configured to execute the computer-readable instructions to select the at least one kernel intermediate value based on one or more input features values included in the input feature map.

6. The neural network processor of claim 5, wherein the at least one processor configured to execute the computer-readable instructions to

store an output intermediate value,

shift the output intermediate value by 1-bit to generate a shifted output intermediate value, and

generate an updated output intermediate value by summing the at least one kernel intermediate value and the shifted output intermediate value in response to determining that a summation operation should be performed.

7. The neural network processor of claim 6, wherein the at least one processor configured to execute the computer-readable instructions to determine that the summation operation should not be performed based on at least one most significant bit value of the one or more input feature values.

8. The neural network processor of claim 6, wherein the at least one processor configured to execute the computer-readable instructions to output the updated output intermediate value, based on the at least one kernel intermediate value corresponding to at least one least significant bit value of the one or more input feature values.

9. The neural network processor of claim 5, wherein

the at least one processor configured to execute the computer-readable instructions to

store an output intermediate value,

shift the output intermediate value by 1-bit to generate a shifted output intermediate value, and

generate an updated output intermediate value by performing a determined type of operation on the at least one kernel intermediate value and the shifted output intermediate value.

10. The neural network processor of claim 9, wherein at least one processor configured to execute the computer-readable instructions to compensate for an output value generated by summing an offset value and a final output intermediate value based on the updated output intermediate value.

11. The neural network processor of claim 10, wherein the offset value is equal to a value obtained by dividing a sum of the plurality of weight values by ‘

2’

.

12. The neural network processor of claim 1, wherein the at least one processor configured to execute the computer-readable instructions to

select a group of kernel intermediate values from among the plurality of kernel intermediate values based on a plurality of input feature values included in the input feature map, the group of kernel intermediate values including the at least one kernel intermediate value, and

perform an arithmetic operation using the group of kernel intermediate values.

13. A convolution operation method of a neural network processor for performing a neural network operation, the convolution operation method comprising:

generating a plurality of kernel intermediate values by performing an operation using a plurality of weight values included in kernel data;

selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on one or more input feature values included in an input feature map; and

generating an updated output intermediate value by performing at least one operation using the at least one kernel intermediate value and an output intermediate value.

14. The convolution operation method of claim 13, further comprising:

outputting the updated output intermediate value based on the at least one kernel intermediate value corresponding to at least one least significant bit value of the one or more input feature values.

15. The convolution operation method of claim 13, wherein the generating the updated output intermediate value comprises:

shifting a previous output intermediate value by one or more bits to generate a shifted output intermediate value, and

summing the shifted output intermediate value and the at least one kernel intermediate value.

16. The convolution operation method of claim 13, further comprising:

outputting an output value generated by summing the updated output intermediate value and an offset value determined based on the plurality of weight values and at least one least significant bit value of the one or more input feature values.

17. The convolution operation method of claim 13, wherein the selecting the at least one kernel intermediate value comprises:

selecting a group of kernel intermediate values among the plurality of kernel intermediate values based on one or more upper bit values of the one or more input feature values when each of the one or more input features values comprises two or more bits, and

selecting a final kernel intermediate value based on one or more a least-significant bit value of the one or more input feature values.

18. A neural network processor for performing a neural network operation, the neural network processor comprising:

a memory storing computer-readable instructions and a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and

at least one processor configured to execute the computer-readable instructions to

perform a convolution operation based on an input feature map and the plurality of kernel intermediate values, and

select a first kernel intermediate value from among the plurality of kernel intermediate values based on one or more input feature values included in the input feature map.

19. The neural network processor of claim 18, wherein at least one processor configured to execute the computer-readable instructions to

store an output intermediate value,

shift the output intermediate value one or more bits to generate a shifted output intermediate value, and

generate an updated output intermediate value by summing the first kernel intermediate value and the shifted output intermediate value.

20. The neural network processor of claim 18, wherein

the kernel data comprises N weight values, N being a natural number, and

each of the plurality of kernel intermediate values generated by an inner product of a first vector formed by the plurality of weight values and a second vector of one or more elements having N columns in which

each element among the one or more elements is ‘

0’

or ‘

1’

, or

each element among the one or more elements is ‘

−

1’

or ‘

1’

.