ARCHITECTURE FOR ORDERED WRITE OF DATA COLLECTED IN PARALLEL
First Claim
1. A computer-implemented method of performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the method comprising:
- processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis and correspond with two or more paths in an integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths;
determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data;
consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and
writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets.
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Accused Products
Abstract
A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.
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Citations
20 Claims
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1. A computer-implemented method of performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the method comprising:
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processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis and correspond with two or more paths in an integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths; determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data; consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development, the system comprising:
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a memory device configured to store two or more data sets resulting from timing analysis of an integrated circuit and corresponding with two or more paths in the integrated circuit, each path including a set of interconnected components; two or more processors configured to process the two or more data sets in parallel, wherein the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths; and a write processor configured to determine a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data, to determine whether the next timing analysis data is available by consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets, and to write the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A computer program product for performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
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processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis of an integrated circuit and correspond with two or more paths in the integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths; determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data; consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification