SIMULATION SYSTEM AND METHOD

• US 20200134116A1
• Filed: 12/19/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Application

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: CHANG, Yeong-Jar, LEE, Jen-Hsiang, LU, Liang-Ying
• Application Number:
  US16/226,501
• Publication Number:
  US 20200134116A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A simulation system includes an application, a chip model and an off-chip model. The application is configured to generate a corresponding instruction set in accordance with an application situation of a simulation circuit, wherein the simulation circuit includes a chip. The chip model receives the instruction set as an input to simulate operation of at least one intellectual property core of the chip via high-level languages in accordance with the at least one intellectual property core of the chip and to generate a power consumption and an I/O logic signal of the chip. The off-chip model constructs one or more orders of RLCG circuit cascading models in accordance with all or part of the off-chip model abstracted by the S parameter. The application program and the RLCG circuit cascading model are integrated for simulating and analyzing power integrity and signal integrity of the simulation system.

Claims

1. A simulation system, comprising:

an application program, configured to generate a corresponding instruction set in accordance with an application situation of a simulation circuit;

wherein the simulation circuit comprises a chip;

a chip model, configured to receive the instruction set as an input to simulate operation of at least one intellectual property core of the chip in accordance with the at least one intellectual property core of the chip and to generate a power consumption and an I/O logic signal of the chip; and

an off-chip model, configured to construct one or more orders of RLCG (resistor-inductor-capacitor-conductor) circuit cascading models in accordance with all or part of the off-chip model abstracted by a S parameter;

wherein the application program and the RLCG circuit cascading model are integrated for simulating and analyzing power integrity and signal integrity of the simulation circuit.

2. The simulation system as claimed in claim 1, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models, comprising:

searching for at least one resonant frequency in accordance with all or part of the off-chip model abstracted by the S parameter;

adjusting values of a capacitor and a inductor corresponding to at least one circuit model in accordance with the at least one resonant frequency, so that an impedance difference between each of the at least one circuit model in the one or more orders of RLCG circuit cascading models and all or part of the off-chip model abstracted by the S parameter is at a minimum at a corresponding resonant frequency.

3. The simulation system as claimed in claim 1, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models, further comprising:

adjusting the values of the resistor and the conductor corresponding to at least one circuit model in accordance with at least two resonant frequencies, so that an impedance difference between each of the at least one circuit model in the one or more orders of RLCG circuit cascading models and all or part of the off-chip model abstracted by the S parameter is at a minimum between two corresponding adjacent resonant frequencies.

4. The simulation system as claimed in claim 1, wherein the application program and the RLCG circuit cascading model are integrated, comprising:

compiling the RLCG cascading model from SystemC-AMS to a first code;

compiling the chip model from SystemC to a second code;

cascading the first code and the second code and inputting a signal generated by the application program; and

after calculating, the RLCG circuit cascading model can receive the power consumption and the I/O logic signal generated by the simulation system.

5. The simulation system as claimed in claim 1, wherein the power consumption of the chip generated by the chip model is used for analyzing power integrity, and the I/O logic signal of the chip is used for analyzing signal integrity.

6. The simulation system as claimed in claim 1, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models for abstracting all or part of the off-chip model to replace the S parameter.

7. The simulation system as claimed in claim 1, wherein the application program, the instruction set, the chip model, and the off-chip model can be accomplished using high-level languages.

8. A simulation method, implementing an application program to generate a corresponding instruction set in accordance with an application situation of a simulation circuit, wherein the simulation circuit comprises a chip, comprising:

generating a chip model configured to receive the instruction set as an input to simulate operation of at least one intellectual property core of the chip via high-level languages in accordance with the at least one intellectual property core of the chip and to generate a power consumption and an I/O logic signal of the chip;

generating an off-chip model configured to construct one or more orders of RLCG (resistor-inductor-capacitor-conductor) circuit cascading models in accordance with all or part of the off-chip model abstracted by a S parameter; and

integrating the application program and the RLCG circuit cascading model for simulating and analyzing power integrity and signal integrity of the simulation circuit.

9. The simulation method as claimed in claim 8, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models, comprising:

searching for at least one resonant frequency in accordance with all or part of the off-chip model abstracted by the S parameter;

adjusting the values of a capacitor and a inductor corresponding to at least one circuit model in accordance with the at least one resonant frequency, so that an impedance difference between each of the at least one circuit model in the one or more orders of RLCG circuit cascading models and all or part of the off-chip model abstracted by the S parameter is at a minimum at a corresponding resonant frequency.

10. The simulation method as claimed in claim 8, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models, further comprising:

adjusting the values of a resistor and a conductor corresponding to at least one circuit model in accordance with at least two resonant frequencies, so that an impedance difference between each of the at least one circuit model in the one or more orders of RLCG circuit cascading models and all or part of the off-chip model abstracted by the S parameter is at a minimum between two corresponding adjacent resonant frequencies.

11. The simulation method as claimed in claim 8, wherein the application program and the RLCG circuit cascading model are integrated, comprising:

compiling the RLCG cascading model from SystemC-AMS to a first code;

compiling the chip model from SystemC to a second code;

cascading the first code and the second code and inputting a signal generated by the application program; and

after calculating, the RLCG circuit cascading model can receive the power consumption and the I/O logic signal generated by the simulation system.

12. The simulation method as claimed in claim 8, wherein the power consumption of the chip generated by the chip model is used for analyzing power integrity, and the I/O logic signal of the chip is used for analyzing signal integrity.

13. The simulation method as claimed in claim 8, wherein the off-chip model is configured to construct one or more orders of RLCG circuit cascading models for abstracting all or part of the off-chip model to replace the S parameter.

14. The simulation method as claimed in claim 8, wherein the application program, the instruction set, the chip model, and the off-chip model can be accomplished using high-level languages.