INTEGRATED CIRCUIT FIN LAYOUT METHOD, SYSTEM, AND STRUCTURE

• US 20200134122A1
• Filed: 10/11/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Po-Hsiang, CHEN, Sheng-Hsiung, KO, Chih-Hsin, CHANG, Fong-Yuan, WANN, Clement Hsingjen, TIEN, Li-Chun, HSU, Chia-Ming
• Granted Patent: US 11,080,453 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Claims

1. A method of operating an integrated circuit (IC) manufacturing system, the method comprising:

determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell;

positioning the first active region along a cell height direction in an IC layout diagram of the cell, the first active region comprising a first total number of fins extending in a direction perpendicular to the cell height direction;

positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and comprising a second total number of fins less than the first total number of fins and extending in the direction; and

storing the IC layout diagram of the cell in a cell library.

2. The method of claim 1, wherein the determining whether the n-type active region or the p-type active region is the first active region comprises executing a circuit simulation based on a layout design corresponding to the IC layout diagram of the cell.

3. The method of claim 1, wherein

the positioning the first active region comprises positioning the first active region a first distance from a first cell border segment along the cell height direction,

the positioning the second active region comprises positioning the second active region the first distance along the cell height direction from a second cell border segment opposite the first cell border segment, and

the first distance corresponds to a first minimum spacing rule.

4. The method of claim 3, wherein one or both of the positioning the first active region or the positioning the second active region comprises separating the first and second active regions by a second distance along the cell height region greater than or equal to a second minimum spacing rule.

5. The method of claim 4, wherein

the positioning the first active region comprises positioning the first active region having a first height in the cell height direction corresponding to the first total number of fins,

the positioning the second active region comprises positioning the second active region having a second height in the cell height direction corresponding to the second total number of fins, and

the first and second minimum spacing rules, the first and second heights, a height of the cell in the cell height direction, and the first and second distances are related such that a sum of the first and second total numbers of fins is a maximum number of fins capable of being included in the positioning the first and second active regions in the IC layout diagram of the cell.

6. The method of claim 1, wherein

the first total number of fins is equal to three, and

the second total number of fins is equal to two.

7. The method of claim 1, further comprising receiving the IC layout diagram of the cell, wherein the positioning the first active region in the cell comprises increasing a height of an existing active region of the cell along the cell height direction.

8. The method of claim 1, further comprising:

positioning a third active region in the cell along the cell height direction, the third active region being a same n-type or p-type as the second active region and comprising the first total number of fins; and

positioning a fourth active region in the cell along the cell height direction, the fourth active region being a same n-type or p-type as the first active region and comprising the second total number of fins.

9. The method of claim 1, further comprising, based on the IC layout diagram of the cell, at least one of:

fabricating a semiconductor mask or component, or

performing one or more manufacturing operations.

10. An integrated circuit (IC) layout diagram generation system comprising:

a processor; and

a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to;

arrange a first plurality of fin tracks into a first subset comprising a first total number of fin tracks corresponding to a first type of an n-type or a p-type, and a second subset comprising a second total number of fin tracks corresponding to a second type of the n-type or the p-type, wherein

the first plurality of fin tracks extend in a first direction, and

the first total number is greater than the second total number;

arrange a second plurality of fin tracks extending in the first direction into a first subset comprising the first total number of fin tracks corresponding to the second type, and a second subset comprising the second total number of fin tracks corresponding to the first type;

abut the second subset of the first plurality of fin tracks with the first subset of the second plurality of fin tracks along a second direction perpendicular to the first direction; and

generate an IC layout diagram based on the first plurality of fin tracks and the second plurality of fin tracks.

11. The IC layout diagram generation system of claim 10, wherein

the first total number of fin tracks is equal to three and the second total number of fin tracks is equal to two, or

the first total number of fin tracks is equal to two and the second total number of fin tracks is equal to one.

12. The IC layout diagram generation system of claim 10, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:

place a cell in the IC layout diagram by aligning a fin configuration of the cell with at least one of the first plurality of fin tracks or the second plurality of fin tracks along the first direction.

13. The IC layout diagram generation system of claim 10, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:

align, along the first direction, each fin track of a third plurality of fin tracks with a corresponding fin track of one of the first plurality of fin tracks or the second plurality of fin tracks, wherein

the third plurality of fin tracks comprises a first subset comprising the second total number of fin tracks corresponding to the first type and a second subset comprising the second total number of fin tracks corresponding to the second type, and

the third plurality of fin tracks and the one of the first plurality of fin tracks or the second plurality of fin tracks are separated by a gap.

14. The IC layout diagram generation system of claim 13, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:

receive a plurality of cells, each cell of the plurality of cells having a cell type; and

align a fin configuration of each cell of the plurality of cells along the first direction with one of the first plurality of fin tracks, the second plurality of fin tracks, or the third plurality of fin tracks based on the cell type of the each cell of the plurality of cells.

15. The IC layout diagram generation system of claim 14, wherein the cell types are based on timing criteria associated with one or more logic functions.

16. The IC layout diagram generation system of claim 13, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to:

receive a cell having a total number of fins equal to zero; and

place the cell in the gap and adjacent to each of the third plurality of fin tracks and the one of the first plurality of fin tracks or the second plurality of fin tracks.

17. An integrated circuit (IC) structure comprising:

a first plurality of fins of a first type of an n-type or a p-type;

a second plurality of fins of a second type of the n-type or the p-type, the second plurality of fins being parallel to and adjacent to the first plurality of fins;

a third plurality of fins of the second type, the third plurality of fins being parallel to and adjacent to the second plurality of fins; and

a fourth plurality of fins of the first type, the fourth plurality of fins being parallel to and adjacent to the third plurality of fins,

wherein

the first plurality of fins and the third plurality of fins have a same first number of fins,

the second plurality of fins and the fourth plurality of fins have a same second number of fins, and

the first number is greater than the second number.

18. The IC structure of claim 17, wherein the first number is equal to three and the second number is equal to two.

19. The IC structure of claim 17, further comprising a fifth plurality of fins having the second number of fins, wherein the fins of the fifth plurality of fins are the first type, aligned with a subset of the first plurality of fins, and separated from the first plurality of fins by a fin discontinuity region.

20. The IC structure of claim 19, further comprising a sixth plurality of fins having the second number of fins, wherein the fins of the sixth plurality of fins are parallel to and adjacent to the fifth plurality of fins.