SEMICONDUCTOR DEVICE WITH FILLER CELL REGION, METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME

• US 20200134125A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Po-Hsiang, LIU, Chin-Chou, CHEN, Sheng-Hsiung, CHANG, Fong-Yuan, ZHUANG, Hui-Zhong, WANG, Meng-Hsueh, CHENG, Yi-Kan, CHEN, Chun-Chen
• Granted Patent: US 11,138,360 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00

Abstract

A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

Claims

1. A method of manufacturing a semiconductor device, the method comprising, for a layout diagram stored on a non-transitory computer-readable medium and including a first level of metallization (M_1st level) representing a first layer of metallization in the semiconductor device, generating the layout diagram including:

identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell in a first direction, the filler and first functional cells representing corresponding non-functional and first functional cell regions in the semiconductor device;

the first functional cell including;

first and second boundaries relative to the first direction (side boundaries), the second side boundary substantially abutting the filler cell;

first wiring patterns extending substantially in the first direction in the M_1st level and representing corresponding first conductors in the first functional cell region; and

first and second groups of cut patterns overlying corresponding portions of the first wiring patterns, the first group overlapping the second side boundary;

adjusting, in the first direction, one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell; and

wherein each of the side boundaries extends substantially in a second direction substantially perpendicular to the first direction.

2. The method of claim 1, further comprising:

based on the layout diagram, at least one of;

(A) making one or more photolithographic exposure;

(B) fabricating one or more semiconductor masks;

or

(C) fabricating at least one component in a layer of a semiconductor integrated circuit.

3. The method of claim 1, wherein:

the layout diagram further includes a first level of interconnection (VIA_1st level) overlying the M_1 st level and representing a first layer of interconnection overlying the first layer of metallization in the semiconductor device; and

the generating the layout diagram further includes;

generating a first via pattern in the V_1st level; and

locating the first via pattern correspondingly over a corresponding first one of the first elongated wiring patterns such that the first via pattern is located in the filler cell.

4. The method of claim 3, wherein:

the layout diagram further includes a second level of metallization (M_2nd level) overlying the VIA_1st level and representing a second layer of interconnection overlying the first layer of interconnection in the semiconductor device; and

the generating the layout diagram further includes;

generating a second wiring pattern in the M_2nd level which extends substantially in the second direction; and

locating the second wiring pattern correspondingly over the first via pattern such that the second wiring pattern is located in the filler cell.

5. The method of claim 4, wherein:

a size, in the first direction, of the filler cell is one contacted poly pitch (CPP).

6. The method of claim 4, wherein:

a size, in the first direction, of the filler cell is at least two multiples of a contacted poly pitch (CPP); and

the generating the layout diagram further includes;

generating a second via pattern in the V_1st level; and

locating the second via pattern correspondingly over a corresponding second one of the first elongated wiring patterns such that the second via pattern is located in the filler cell;

generating a third wiring pattern in the M_2nd level which extends substantially in the second direction; and

locating the third wiring pattern correspondingly over the second via pattern such that the third wiring pattern is located in the filler cell.

7. The method of claim 1, wherein:

a size, in the first direction, of the filler cell is one contacted poly pitch (CPP).

8. The method of claim 1, wherein:

the first elongated wiring patterns correspond to either odd ones or even ones of the first wiring patterns.

9. The method of claim 1, wherein:

the first elongated wiring patterns correspond to all of the first wiring patterns.

10. The method of claim 1, wherein:

the filler cell includes third and fourth side boundaries, the third side boundary substantially abutting the second side boundary of the first functional cell;

the layout diagram further includes;

a second functional cell substantially abutting the fourth side of the filler cell, the second functional cell representing a second functional cell region in the semiconductor device;

the second functional cell including;

fifth and sixth side boundaries, the fifth side boundary substantially abutting the fourth side boundary of the filler cell;

second wiring patterns extending substantially in the first direction in the M_1st level and representing corresponding second conductors in the second functional cell region;

third and fourth groups of cut patterns overlying corresponding portions of the second wiring patterns, and being substantially aligned with the corresponding fifth and sixth side boundaries so as to render the corresponding second wiring patterns as being intra-cell; and

the method further comprises;

adjusting, in the first direction, one or more locations of corresponding one or more selected cut patterns of the third group thereby correspondingly elongating one or more selected ones of the second wiring patterns so as to be corresponding second elongated wiring patterns which extend across the fifth side boundary of the first functional cell into the filler cell.

11. The method of claim 10, wherein:

the first elongated wiring patterns and the second elongated wiring patterns define corresponding first and second profiles, relative to the first direction, the second profile being a substantially complementary shape with respect to the first profile.

12. The method of claim 10, wherein:

at least one of the first elongated wiring patterns and at least one of the second elongated wiring patterns are substantially collinear and, relative to the second direction, overlapping so as to collectively represent a conductor which extends from the first functional cell region through the non-functional cell region and into the second functional cell region of the semiconductor device.

13. A system for manufacturing a semiconductor device, the system comprising:

at least one processor; and

at least one memory including computer program code for one or more programs;

wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute, for a layout diagram stored on a non-transitory computer-readable medium and including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) correspondingly representing a first layer of metallization and an overlying first layer of interconnection in the semiconductor device, generating the layout diagram including;

identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell in a first direction, the filler and first functional cells representing corresponding non-functional and first functional cell regions in the semiconductor device;

the first functional cell including;

first and second boundaries relative to the first direction (side boundaries), the second side boundary substantially abutting the filler cell;

first wiring patterns extending substantially in the first direction in the M_1st level and representing corresponding first conductors in the first functional cell region; and

first and second groups of cut patterns overlying corresponding portions of the first wiring patterns, the first group overlapping the second side boundary;

adjusting, in the first direction, one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell;

generating a first via pattern in the V_1st level; and

locating the first via pattern correspondingly over a corresponding first one of the first elongated wiring patterns such that the first via pattern is located in the filler cell; and

wherein each of the side boundaries extends substantially in a second direction substantially perpendicular to the first direction.

14. The system of claim 13, further comprising at least one of:

a masking facility configured to fabricate one or more semiconductor masks based on based on the layout diagram;

or

a fabricating facility configured to fabricate at least one component in a layer of a semiconductor integrated circuit based on the layout diagram.

15. The system of claim 13, wherein:

the layout diagram further includes a second level of metallization (M_2nd level) overlying the VIA_1st level and representing a second layer of metallization overlying the first layer of interconnection in the semiconductor device; and

the generating the layout diagram further includes;

generating a second wiring pattern in the M_2nd level which extends substantially in the second direction; and

locating the second wiring pattern correspondingly over the first via pattern such that the second wiring pattern is located in the filler cell.

16. The system of claim 15, wherein:

a size, in the first direction, of the filler cell is one contacted poly pitch (CPP).

17. The system of claim 15, wherein:

a size, in the first direction, of the filler cell is at least two multiples of a contacted poly pitch (CPP); and

the generating the layout diagram further includes;

generating a second via pattern in the V_1st level; and

locating the second via pattern correspondingly over a corresponding second one of the first elongated wiring patterns such that the second via pattern is located in the filler cell;

generating a third wiring pattern in the M_2nd level which extends substantially in the second direction; and

locating the third wiring pattern correspondingly over the second via pattern such that the third wiring pattern is located in the filler cell.

18. The system of claim 17, wherein:

the filler cell includes third and fourth side boundaries, the third side boundary substantially abutting the second side boundary of the first functional cell;

the layout diagram further includes;

a second functional cell substantially abutting the fourth side of the filler cell, the second functional cell representing a second functional cell region in the semiconductor device;

the second functional cell including;

fifth and sixth side boundaries, the fifth side boundary substantially abutting the fourth side boundary of the filler cell;

second wiring patterns extending substantially in the first direction in the M_1st level and representing corresponding second conductors in the second functional cell region;

third and fourth groups of cut patterns overlying corresponding portions of the second wiring patterns, and being substantially aligned with the corresponding fifth and sixth side boundaries so as to render the corresponding second wiring patterns as being intra-cell; and

the method further comprises;

adjusting, in the first direction, one or more locations of corresponding one or more selected cut patterns of the third group thereby correspondingly elongating one or more selected ones of the second wiring patterns so as to be corresponding second elongated wiring patterns which extend across the fifth side boundary of the first functional cell into the filler cell; and

the first elongated wiring patterns and the second elongated wiring patterns defining corresponding first and second profiles, relative to the first direction, the second profile being a substantially complementary shape with respect to the first profile.

19. A semiconductor device comprising:

a first layer of metallization (M_1st layer) in the semiconductor device; and

a filler cell region and a first functional cell region substantially abutting the filler cell region in a first direction; and

wherein;

the first functional cell region including;

first conductors extending substantially in the first direction in the M_1st laver;

the first functional cell region further including;

a first conductive structure coupling a first one of the first conductors to a source/drain region of a transistor;

or

a second conductive structure coupling a second one of the first conductors to a gate structure of a transistor;

one or more selected ones of the first conductors being elongated, relative to first direction, so as to extend beyond the first functional cell region into the filler cell region; and

the filler cell region not including;

a third conductive structure coupling a conductive segment in the M_1st layer to a source/drain region of a transistor;

nor

a fourth second conductive structure coupling a conductive segment in the M_1st layer to a gate structure of a transistor.

20. The semiconductor device of claim 19, further comprising:

a first layer of interconnection (VIA_1st layer) overlying the M_1st layer; and

a first via structure in the V_1st layer, the first via structure being located over a corresponding first one of the selected ones of the first conductors and in the filler cell region.