REDUCED AREA STANDARD CELL ABUTMENT CONFIGURATIONS

• US 20200134126A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LU, Chi-Yu, ZHUANG, Hui-Zhong, TIEN, Li-Chun, SUE, Pin-Dai, KO, Yi-Hsin
• Granted Patent: US 11,216,608 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.

Claims

1. A method of designing a semiconductor device, the method comprising:

retrieving a layout design file;

searching the layout design file for a vertical abutment between a first standard cell block and second cell block;

analyzing the vertical abutment between the first standard cell block and second cell block and, in response to identifying a mismatch between the first standard cell block and the second cell block;

selecting a first modified cell block that reduces the mismatch, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment; and

replacing the first standard cell block with the first modified cell block to obtain a first modified layout design.

3. The method of designing a semiconductor device according to claim 1, further comprising:

selecting a second modified cell block that reduces the mismatch, the second modified cell comprising a second abutment region having a continuous active region along a second axis parallel to the edge of the vertical abutment; and

replacing the second cell block with the second modified cell block to obtain a second modified layout design.

4. The method of designing a semiconductor device according to claim 1, further comprising:

selecting the first modified cell block that comprises a second active region arranged parallel to and inwardly from the continuous active region.

5. The method of designing a semiconductor device according to claim 1, further comprising:

selecting the first modified cell block that comprises a plurality of active regions arranged parallel to and inwardly from the continuous active region.

6. The method of designing a semiconductor device according to claim 5, further comprising:

selecting the first modified cell block that comprises

a first discontinuous active region having an average active region length of L₁; and

a second discontinuous active region arranged inwardly from the first discontinuous active region and having an average active region length of L₂, wherein L₁≠

L₂

7. The method of designing a semiconductor device according to claim 5, further comprising:

selecting the first modified cell block wherein at least one of the plurality of active regions is continuous.

8. The method of designing a semiconductor device according to claim 1, further comprising:

reanalyzing the vertical abutment between the first modified cell block and the second cell block and, in response to identifying a mismatch between the first modified cell block and the second cell block;

selecting a second modified cell block that reduces the mismatch, the second modified cell block comprising a second abutment region having a continuous active region along a second axis parallel to the abutment edge; and

replacing the first modified cell block with the second modified cell block to obtain a second modified layout design.

9. The method of designing a semiconductor device according to claim 1, further comprising:

retrieving the first modified cell block from a cell block library.

10. The method of designing a semiconductor device according to claim 1, further comprising:

analyzing the layout design file for a horizontal abutment between the first standard cell block and a third cell block and, when a second mismatch is identified between the first standard cell block and the third cell block;

incorporating a second modified cell block to reduce the second mismatch, wherein the second modified cell block includes a horizontal transition region having a plurality of conductive structures arranged perpendicular to a second axis parallel to the horizontal abutment edge.

11. The method of designing a semiconductor device according to claim 1, further comprising:

selecting a first modified abutment region that reduces the mismatch, the first modified abutment region comprising a continuous active region along a first axis parallel to an abutment edge; and

replacing the first abutment region with the first modified abutment region to obtain a first modified layout design.

2. The method of designing a semiconductor device according to claim 2, further comprising:

selecting the second cell block from a library of standard cell blocks.

12. A semiconductor device comprising:

a first modified cell block having a first modified abutment region;

a second cell block having a second abutment region;

the first modified cell block and the second cell block are arranged to form a vertical abutment;

wherein the first modified abutment region comprising a first continuous active region along a first axis parallel to a vertical abutment edge; and

wherein the first modified abutment region is positioned directly adjacent the second abutment region to reduce a total device area occupied by the first modified cell block and the second cell block.

13. The semiconductor device according to claim 12, wherein:

the second cell block comprises a second modified cell block; and

the second modified cell block includes a second modified abutment region having a second continuous active region along a second axis parallel to the vertical abutment edge.

14. The semiconductor device according to claim 12, wherein:

the first modified abutment region comprises a second active region arranged parallel to and inwardly from the first continuous active region.

15. The semiconductor device according to claim 14, wherein:

the first modified abutment region comprises a first plurality of active regions arranged parallel to and inwardly from the first continuous active region.

16. The semiconductor device according to claim 15, wherein:

the first plurality of active regions arranged parallel comprises a first discontinuous active region having an average active region length of L₁; and

a second discontinuous active region arranged inwardly from the first discontinuous active region and having an average active region length of L₂.

17. The semiconductor device according to claim 14, wherein:

second active region is continuous.

18. The semiconductor device according to claim 16, wherein:

L₁>

L₂.

19. The semiconductor device according to claim 12, further comprising:

a transition region arranged perpendicular to the vertical abutment edge, the transition region comprising a plurality of conductive elements arranged in parallel.

20. A semiconductor device comprising:

a first modified cell block having a first modified vertical abutment region and a first horizontal abutment region;

a second cell block having a second vertical abutment region;

a third cell block having a second horizontal abutment region;

the first modified cell block and the second cell block are arranged to form a vertical abutment;

wherein the first modified vertical abutment region comprising a continuous active region along a first axis parallel to a vertical abutment edge;

wherein the first modified vertical abutment region is positioned directly adjacent the second vertical abutment region, thereby reducing total device area; and

wherein the first and second horizontal abutment regions cooperate to form a combined horizontal abutment region arranged perpendicular to the vertical abutment edge, the combined horizontal abutment comprising a plurality of conductive elements arranged in parallel.