INTEGRATED CIRCUIT DESIGN

• US 20200134127A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: GANGWAR, Anup, AGARWAL, Nitin Kumar, Naga Ambica PRASAD, Honnahuggi Harinath Venkata
• Granted Patent: US 10,628,626 B1
• Time in Patent Office: Days
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/32 Circuit design at the digital level reconfigurable circuits G06F30/34
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by:

• • (i) detecting two or more connected groups of the data handling nodes in which all of the data handling nodes in a given group have the same provisional data width and in which, for each given group, the provisional data width of data handling nodes in that group is different to the provisional data width of data handling nodes in a group connected to the given group;
  • (ii) selecting two or more of the groups to be merged, in dependence upon a cost function; and
  • (iii) merging the selected two or more groups, the merging comprising assigning a provisional data width to all of the data handling nodes in the selected two or more groups equal to one of the provisional data widths amongst the selected two or more groups; and
  • using the computer, providing one or more other components in the layout including at least a data width resizing component between each pair of groups having different respective provisional data widths.

Claims

1. A computer-implemented method of integrated circuit design, the method comprising:

using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node;

using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path;

using the computer, performing one or more iterations of modifying the integrated circuit topology by;

(i) detecting two or more connected groups of the data handling nodes in which all of the data handling nodes in a given group have the same provisional data width and in which, for each given group, the provisional data width of data handling nodes in that group is different to the provisional data width of data handling nodes in a group connected to the given group;

(ii) selecting two or more of the groups to be merged, in dependence upon a cost function; and

(iii) merging the selected two or more groups, the merging comprising assigning a provisional data width to all of the data handling nodes in the selected two or more groups equal to one of the provisional data widths amongst the selected two or more groups; and

using the computer, providing one or more other components in the layout including at least a data width resizing component between each pair of groups having different respective provisional data widths.

2. The method of claim 1 comprising:

ordering the groups by an ordering criterion;

selecting a given group from the ordered groups; and

selecting one or more merge candidate groups from one or more other groups connected to the given group.

3. The method of claim 2 comprising performing two or more iterations of the modifying step, and selecting at least two different given groups for different iterations according to the group ordering criterion.

4. The method of claim 2, in which:

the data handling nodes are connected to one another by data handling node links; and

the ordering criterion is a function of the number of data handling node links connecting the data handling nodes in each group.

5. The method of claim 2, in which the one or more merge candidate groups have a lower provisional data width than the given group.

6. The method of claim 1, in which the provisional data width of any given data handling node is increased by, or unchanged as a result of, any given iteration of the modifying step.

7. The method of to claim 1, in which the cost function is configured to generate a cost value which indicates a greater cost in response to an increase in one or more parameters selected from the list consisting of:

power usage of data handling nodes and connections;

physical area required to fabricate the data handling nodes and data handling node links;

number of logic components required to fabricate the data handling nodes; and

latency of the data communication paths.

8. The method of claim 7, comprising performing successive iterations of the modifying step, in which each iteration reduces the cost indicated by the cost value of the cost function, until no further iterations are possible which reduce the cost indicated by the cost value of the cost function.

9. The method of claim 7, comprising assigning a respective weighting to each parameter of the cost function, the weighting for a parameter being generated as a result of applying a weighting function to that parameter.

10. The method of claim 1, in which the data handling nodes are configured within more than one power domain.

11. The method of claim 10, in which one or more of the other components provided is a power converter component.

12. The method of claim 1, in which data handling nodes are configured within more than one clock domain.

13. The method of claim 12, in which one or more of the other components provided is a clock domain converter component.

14. The method of claim 1, in which, for a data communication path having, in the layout, at least a threshold path length, the routing nodes of that data communication path comprise a pipeline component.

15. The method of claim 1, in which the merging step comprises merging the selected two or more groups, the merging comprising assigning a provisional data width to all of the data handling nodes in the selected two or more groups equal to the highest provisional data width amongst the selected two or more groups.

16. The method of claim 4, in which the ordering criterion is an order of the number of data handling node links connecting the data handling nodes in each group.

17. The method of claim 16, comprising selecting the group with the largest number of data handling node links as the given group for the first iteration of the modifying step.

18. The method of claim 1, comprising the step of:

fabricating an integrated circuit layout according to the integrated circuit design.

19. An integrated circuit having an integrated circuit design produced by the following computer-implemented method:

using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node;

using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path;

using the computer, performing one or more iterations of modifying the integrated circuit topology by;

(i) detecting two or more connected groups of the data handling nodes in which all of the data handling nodes in a given group have the same provisional data width and in which, for each given group, the provisional data width of data handling nodes in that group is different to the provisional data width of data handling nodes in a group connected to the given group;

(ii) selecting two or more of the groups to be merged, in dependence upon a cost function; and

(iii) merging the selected two or more groups, the merging comprising assigning a provisional data width to all of the data handling nodes in the selected two or more groups equal to one of the provisional data widths amongst the selected two or more groups; and

using the computer, providing one or more other components in the layout including at least a data width resizing component between each pair of groups having different respective provisional data widths.

20. A computer program product comprising a non-transitory machine-readable storage medium on which are stored program instructions which, when executed by a computer processor, cause the computer processor to perform a method of integrated circuit design, the method comprising:

detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node;

assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path;

performing one or more iterations of modifying the integrated circuit topology by;

(i) detecting two or more connected groups of the data handling nodes in which all of the data handling nodes in a given group have the same provisional data width and in which, for each given group, the provisional data width of data handling nodes in that group is different to the provisional data width of data handling nodes in a group connected to the given group;

(ii) selecting two or more of the groups to be merged, in dependence upon a cost function; and

(iii) merging the selected two or more groups, the merging comprising assigning a provisional data width to all of the data handling nodes in the selected two or more groups equal to one of the provisional data widths amongst the selected two or more groups; and

providing one or more other components in the layout including at least a data width resizing component between each pair of groups having different respective provisional data widths.