METAL WITH BURIED POWER FOR INCREASED IC DEVICE DENSITY
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Abstract
A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track.
18 Citations
40 Claims
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1-20. -20. (canceled)
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21. A device comprising:
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a double-height cell having routing tracks in a first layer of metallization on an insulating layer, the double-height cell having two sides extending in a first direction and separated by the double-height cell in a second direction perpendicular to the first direction, wherein a first routing track has a first run-side extending in the first direction along the first side of the double-height cell, and a second routing track has a second run-side extending in the first direction along the second side of the double-height cell; a via connection in the insulating layer that connects a terminal of a transistor to one of the routing tracks on the insulating layer, wherein the terminal of the transistor includes one of a gate, a source, or drain of the transistor; a first buried power line, extending in the first direction, underneath the insulating layer, and aligned with the first run-side of the first routing track in the double-height cell; a second buried power line, extending in the first direction, underneath the insulating layer, and aligned with the second run-side of the second routing track in the double-height cell; and a third buried power line, extending in the first direction, underneath the insulating layer, and separated from the first buried power line and the second buried power line at an equal distance to each of the first buried power line and the second buried power line. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A method of manufacturing a semiconductor device, the method comprising, for a layout diagram stored on a non-transitory computer-readable medium and including a first level of metallization representing a first layer of metallization in the semiconductor device, generating the layout diagram including:
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generating a first cell having a first boundary and a second boundary, each of the first boundary and the second boundary extending in a first direction, on opposite sides of the first cell, wherein the first cell includes an irregular polygonal routing track in the first layer of metallization; generating a second cell having a first boundary and a second boundary, each of the first boundary and the second boundary extending in a first direction, on opposite sides of the first cell, wherein the second cell includes an irregular polygonal routing track in the first layer of metallization; aligning the first boundary of the first cell and the first boundary of the second cell to form a common boundary that separates the first cell from the second cell; generating a double-height cell having two cell boundaries, each of the two cell boundaries extending in the first direction, separated by a distance equal to a double cell distance between the second boundary of the first cell and the second boundary of the second cell, wherein a first half of the double-height cell and a second half of the double-height cell each have a height that is a half of a height of the double-height cell; and wherein the double-height cell has a routing track, in the first layer of metallization, that extends from the first half of the double-height cell to the second half of the double-height cell. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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37. A method of designing a layout, the method comprising:
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generating a plurality of first routing tracks assigned to a first color group of the layout; generating a plurality of second routing tracks assigned to a second color group of the layout, wherein a first routing track of the plurality of first routing tracks is between adjacent second routing tracks of the plurality of second routing tracks; and specifying a color stitching region connecting a selected first routing track of the plurality of first routing tracks with a selected second routing track of the plurality of second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track. - View Dependent Claims (38, 39, 40)
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Specification