CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

• US 20200134130A1
• Filed: 07/17/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEI, Cheok-Kei, KAO, Jerry Chang Jui, LIU, Chi-Lin, ZHUANG, Hui-Zhong, JIANG, Zhe-Wei, LI, Chien-Hsing
• Granted Patent: US 10,943,050 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

Claims

1. A method of modifying an integrated circuit layout, comprising:

identifying, in an integrated circuit layout, at least one reverse signal net having a first conductive line at a first position and a second conductive line at a second position;

determining whether the first conductive line and the second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold;

determining whether to move the first conductive line to a third position in the integrated circuit layout; and

adjusting the integrated circuit layout by moving the first conductive line to the third position in the integrated circuit layout in response to determining to move the first conductive line to the third position.

2. The method of claim 1, further comprising inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line to the third position.

3. The method of claim 2, wherein inserting the isolation structure comprises inserting a capacitive isolation structure or additional dielectric material.

4. The method of claim 1, further comprising inserting a capacitive isolation structure at the first position after moving the first conductive line to the third position.

5. The method of claim 1, further comprising inserting at least two isolation structures between the first conductive line and the second conductive line.

6. The method of claim 1, further comprising determining an isolation structure line length, wherein, the integrated circuit layout having the first conductive line with a first line length, and the second conductive line having a second line length,

when the first line length equals the second line length, the isolation structure line length is equal to the first length, and wherein,

when the first line length and the second line length are different lengths, the method further comprises determining whether the isolation structure line length is equal to a longer length of the first or second lengths, or whether the isolation structure line length is between the first length and the second length.

7. A device, comprising:

a reverse signal net in an integrated circuit, wherein the reverse signal net comprises;

a first conductive line as an input line, wherein the first conductive line is configured to carry a first voltage, and

a second conductive line as an output line, wherein the first conductive line and the second conductive line are in a same level of the integrated circuit, and the second conductive line is configured to carry a second voltage logically opposite to the first voltage; and

a first isolation structure between the first conductive line and the second conductive line, wherein a first distance between the first conductive line and the first isolation structure is an integer multiple of an interval, and a second distance between the second conductive line and the first isolation structure is an integer multiple of the interval.

8. The device of claim 7, wherein the first isolation structure is a capacitive isolation structure.

9. The device of claim 8, wherein the first isolation structure is a floating isolation structure.

10. The device of claim 9, further comprising a second isolation structure between the first conductive line and the second conductive line, wherein the second isolation structure is an irrelative-net type isolation structure.

11. The device of claim 8, wherein the first isolation structure is an irrelative-net type isolation structure.

12. The device of claim 7, wherein a first end of the first conductive line, the second conductive line, and the isolation structure align at a first line position, and a second end of the first conductive line, the second conductive line, and the isolation align at a second line position.

13. The device of claim 7, wherein a first end of the first conductive line, the second conductive line, and the isolation structure align at a first line position, and a second end of the first conductive line and the isolation structure align at a second line position, and a second end of the second conductive line is at a third line position different from the second line position, and the second conductive line is shorter than the first conductive line.

14. The device of claim 7, wherein

a first end of the first conductive line, the second conductive line, and the isolation structure align at a first line position, and

the first conductive line has a first length, the second conductive line has a second length different from the first length, and the isolation structure has a third length between the first length and the second length.

15. A computer readable medium having instructions thereon for modifying an integrated circuit, the instructions comprising

identifying, in an integrated circuit layout, at least one reverse signal net having a first conductive line at a first position and a second conductive line at a second position;

determining whether the first conductive line and the second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold;

determining whether to insert an isolation structure to the integrated circuit layout; and

adjusting the integrated circuit layout by inserting an isolation structure between the first conductive line and the second conductive line of the integrated circuit layout.

16. The computer readable medium of claim 15, further comprising instructions for moving the first conductive line to a third position of the integrated circuit layout in response to determining not to insert an isolation structure to the integrated circuit layout.

17. The computer readable medium of claim 15, wherein instructions for inserting the isolation structure further comprise instructions for inserting a dummy isolation structure to the integrated circuit layout.

18. The computer readable medium of claim 15, further comprising instructions for inserting at least two isolation structures between the first conductive line and the second conductive line.

19. The computer readable medium of claim 15, further comprising instructions for inserting a second isolation structure between the first conductive line and a third conductive line of the reverse signal net, wherein the first isolation structure is on a first side of the first conductive line and the second isolation structure is on a second side of the first conductive line.

20. The computer readable medium of claim 15, further comprising determining, whether an isolation structure length is the same as a first line length of the first conductive line or a second line length of the second conductive line, when the first line length and the second line length are different lengths.