TEST PATTERN GENERATION SYSTEMS AND METHODS

• US 20200134131A1
• Filed: 09/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tien, Fu-An, Huang, Hsu-Ting, Liu, Ru-Gun
• Granted Patent: US 11,093,683 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

Claims

1. A test pattern generation system, comprising:

test pattern generation circuitry, which, when in use;

receives a noise image;

generates a pattern image based on the noise image; and

generates a test pattern based on the pattern image, the test pattern being representative of geometric shapes of an electronic device design layout that is free of design rule check (DRC) violations.

2. The system of claim 1, further comprising:

rasterization circuitry, which, when in use;

receives a noise vector; and

generates the noise image as a raster image of the noise vector.

3. The system of claim 1 wherein the test pattern generation circuitry includes:

test generation machine learning circuitry having a generator and a discriminator, each of the generator and the discriminator including a respective trained convolutional neural network, the generator being configured to generate the pattern image based on the noise image, the discriminator being configured to classify the pattern image as representative of a valid layout clip or an invalid layout clip.

4. The system of claim 1, further comprising:

a layout shape database which stores information representative of geometrical shapes of a plurality of features of electronic device layouts,

wherein the test generation circuitry is configured to generate the test pattern by converting one or more shapes in the pattern image into one or more of the geometrical shapes stored in the layout shape database.

5. The system of claim 1, further comprising:

DRC check circuitry configured to analyze the test pattern and determine whether one or more DRC violations are present in the test pattern.

6. The system of claim 5, further comprising:

a test pattern database,

wherein the test pattern generation circuitry is configured to provide the test pattern to the test pattern database for storage in response to the DRC check circuitry determining that the test pattern is free of DRC violations.

7. A method, comprising:

receiving, by test pattern generation circuitry, a noise image representative of random noise;

generating, by the test pattern generation circuitry, a pattern image based on the received noise image; and

generating, by the test pattern generation circuitry, a test pattern based on the pattern image, the test pattern being representative of geometric shapes of an electronic device design layout that is free of design rule check (DRC) violations.

8. The method of claim 7, further comprising:

receiving, by rasterization circuitry, a random noise vector; and

generating, by the rasterization circuitry, the noise image as a raster image of the random noise vector.

9. The method of claim 7, wherein the generating the test pattern includes generating the test pattern by converting one or more shapes in the generated pattern image into one or more geometrical shapes stored in a layout shape database.

10. The method of claim 7, further comprising:

determining, by DRC check circuitry, whether one or more DRC violations are present in the test pattern.

11. The method of claim 10, further comprising:

storing the test pattern in a test pattern database in response to determining that the test pattern is free of DRC violations.

12. The method of claim 10, further comprising:

adjusting, by the test pattern generation circuitry, at least one of a spacing between one or more of the geometric shapes represented by the test pattern or a width of one or more of the geometric shapes represented by the test pattern.

13. A method, comprising:

training a discriminator of a test generation machine learning circuitry by;

providing first training input representative of a first plurality of layout clips to the discriminator, the first plurality of layout clips being layout clips for electronic devices which are known to be free of design rule check (DRC) violations; and

providing second training input representative of a second plurality of layout clips to the discriminator, the second plurality of layout clips being layout clips for electronic devices which are known to include one or more DRC violations; and

modifying parameters of the discriminator based on the training, the discriminator being configured to classify a received input as being representative of a valid layout clip or an invalid layout clip based on the modified parameters.

14. The method of claim 13 wherein the modifying parameters of the discriminator includes modifying at least one of a weight or a bias of a convolutional neural network.

15. The method of claim 13, further comprising:

receiving, by rasterization circuitry, the first plurality of layout clips;

generating, by the rasterization circuitry, the first training input as a first plurality of raster images based on the first plurality of layout clips;

receiving, by the rasterization circuitry, the second plurality of layout clips; and

generating, by the rasterization circuitry, the second training input as a second plurality of raster images based on the second plurality of layout clips.

16. The method of claim 13, further comprising:

training a generator of the test generation machine learning circuitry by;

providing a plurality of random noise images as training input to the generator;

generating, by the generator, first pattern images based on the plurality of random noise images;

generating, by the discriminator, loss information based on the first pattern images generated by the generator, the loss information indicating deviations between classifications of the first pattern images by the discriminator and a valid layout clip classification; and

modifying parameters of the generator based on the loss information.

17. The method of claim 16 wherein the modifying parameters of the generator includes modifying at least one of a weight or a bias of a convolutional neural network.

18. The method of claim 15, further comprising:

receiving, by rasterization circuitry, a plurality of random noise vectors; and

generating, by the rasterization circuitry, the plurality of random noise images as a plurality of raster images based on the plurality of random noise vectors.

19. The method of claim 16, further comprising:

further training the discriminator based on second pattern images generated by the generator while the parameters of the generator are fixed; and

further modifying the parameters of the discriminator based on the further training.

20. The method of claim 19, further comprising:

alternately performing the training the generator and the further training the discriminator a plurality of times.