POWER RAIL WITH NON-LINEAR EDGE

• US 20200134133A1
• Filed: 10/21/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Jung-Chan, CHIANG, Ting-Wei, ZHUANG, Hui-Zhong, LU, Chi-Yu
• Granted Patent: US 11,093,684 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3953 detailed
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method for designing an integrated circuit includes steps of selecting a power rail of a cell, determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection, selecting a power rail portion of the power rail for modification, and modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection. As clearance distances between features in an interconnection structure of an integrated circuit become smaller, manufacturing becomes more difficult and error-prone. Increasing clearance distances improves manufacturability of an integrated circuit. Modifying the shape of an integrated circuit power rail increases clearance distance to and/or around a power rail.

Claims

1. A method, comprising:

selecting a power rail of a cell;

determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection;

selecting a power rail portion of the power rail for modification; and

modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection.

2. The method of claim 1, wherein modifying a shape of the power rail portion includes offsetting the inner edge of the power rail portion, with regard to an inner edge of an unmodified power rail portion, and an outer edge of the power rail portion, with regard to an outer edge of the unmodified power rail portion, in a first direction.

3. The method of claim 1, wherein modifying a shape of the power rail portion includes reducing a width of the power rail portion while maintaining a width of another portion of the power rail.

4. The method of claim 3, wherein reducing a width of the power rail portion includes offsetting an inner edge of the power rail portion in a first direction toward a center of the power rail.

5. The method of claim 4, wherein reducing a width of the power rail further includes offsetting an outer edge of the power rail portion in a second direction toward the center of the power rail.

6. The method of claim 1, wherein modifying a shape of the power rail portion includes removing the power rail portion.

7. The method of claim 1, further comprising:

determining whether to modify a conductive line paired with the power rail;

selecting, upon determining to modify the conductive line paired with the power rail, a conductive line segment for modification;

modifying a shape of at least one conductive line of the cell.

8. The method of claim 7, wherein modifying a shape of at least one conductive line further comprises merging a first conductive line with a second conductive line.

9. The method of claim 7, wherein modifying a shape of at least one conductive line further comprises removing a first conductive line segment.

10. The method of claim 7, wherein modifying a shape of at least one conductive line further comprises increasing a width, in a direction perpendicular to a length of the power rail, one of the at least one conductive line segment.

11. An integrated circuit, comprising:

a source/drain (S/D) line in a cell of the integrated circuit;

a power rail extending over the S/D line, wherein the power rail comprises a first power rail portion and a second power rail portion, and an inner edge of the first power rail portion is offset from an inner edge of the second power rail portion; and

a conductive line over the power rail.

12. The integrated circuit of claim 11, wherein an outer edge of the first power rail portion is aligned with an outer edge of the second power rail portion.

13. The integrated circuit of claim 11, wherein the inner edge of the first power rail portion is offset toward a center of the second power rail portion, with respect to the inner edge of the second power rail portion.

14. The integrated circuit of claim 11, wherein an outer edge of the first power rail portion is offset from an outer edge of the second power rail portion.

15. The integrated circuit of claim 14, wherein the inner edge of the first power rail is offset toward a center of the second power rail portion, with respect to the inner edge of the second power rail portion, and the outer edge of the first power rail is offset toward a center of the power rail with respect to the outer edge of the second power rail portion.

16. The integrated circuit of claim 14, wherein the inner edge of the first power rail is offset toward a center of the second power rail portion, and wherein the outer edge of the first power rail portion is offset away from a center of the second power rail portion, with respect to the inner edge of the second power rail portion.

17. An integrated circuit, comprising

a cell having a source or drain line in a first layer;

a first power rail over the source or drain line in a second layer; and

a conductive line over the power rail, wherein the first power rail is discontinuous across a length of the cell.

18. The integrated circuit of claim 17, wherein the conductive line is continuous across an entire length of the cell.

19. The integrated circuit of claim 17, wherein the first power rail and the conductive line are on different sides of a transition point of the cell.

20. The integrated circuit of claim 17, further comprising a second power rail at an opposite end of the cell from the first power rail, and wherein the second power rail is continuous across an entire length of the cell.