INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF

• US 20200134232A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Abandoned Application

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Nomura, Yoshihisa
• Application Number:
  US16/662,803
• Publication Number:
  US 20200134232A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
• CPC Class Codes: H04L 9/30 Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
• CPC Class Codes: H04L 9/3242 involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An information processing apparatus includes a memory storing a program, a system bus, a first control unit configured to read the program via the system bus and judge whether the read program is altered, a second control unit configured to read the program judged as not being altered, from the memory via the system bus and execute the program, and a clock control unit configured to control a frequency of a clock to be supplied to a module included in the first control unit, wherein the clock control unit controls the frequency of the clock in such a manner that the frequency of the clock from a time point at which the first control unit starts reading the program to a time point at which the reading is finished is higher than the frequency of the clock after the judgement about the program.

Claims

1. An information processing apparatus comprising:

a memory storing a program;

a system bus;

a first control unit configured to read the program stored in the memory via the system bus and judge whether the read program is altered;

a second control unit configured to read the program judged as not being altered, from the memory via the system bus and execute the program; and

a clock control unit configured to control a frequency of a clock to be supplied to the system bus and a frequency of a clock to be supplied to at least one module included in the first control unit,

wherein the clock control unit controls the frequency of the clock to be supplied to the at least one module in such a manner that the frequency of the clock to be supplied to the at least one module, from a time point at which the first control unit starts reading the program to at least a time point at which the reading is finished, is higher than the frequency of the clock to be supplied to the at least one module after the judgement about the program.

2. The information processing apparatus according to claim 1, wherein the clock control unit controls the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit in such a manner that the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit, from the time point at which the first control unit starts reading the program to at least the time point at which the reading is finished, are respectively higher than the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit after the judgement about the program.

3. The information processing apparatus according to claim 1, wherein the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit are different.

4. The information processing apparatus according to claim 3, wherein the frequency of the clock to be supplied to the system bus is higher than the frequency of the clock to be supplied to the first control unit.

5. The information processing apparatus according to claim 1, further comprising a clock supply unit configured to supply the clock to the system bus and the at least one module included in the first control unit,

wherein the clock control unit sets, to the clock supply unit, the frequency of the clock to be supplied by the clock supply unit and controls the frequency of the clock.

6. The information processing apparatus according to claim 1, further comprising a power control unit configured to control supply of power to the first control unit and the second control unit,

wherein the power control unit supplies power to the first control unit and does not supply power to the second control unit from the time point at which the first control unit starts reading the program to a time point at which the judgement is finished, and after the judgement is finished, the power control unit supplies power to the first control unit and the second control unit.

7. The information processing apparatus according to claim 1,

wherein the memory stores a signature of the program that is encrypted with a private key,

wherein the first control unit includes

a calculation unit configured to calculate the signature of the program read from the memory via the system bus,

a reading unit configured to read the encrypted signature from the memory, and

a decryption unit configured to decrypt the read encrypted signature with a public key, and

wherein the first control unit judges whether the program stored in the memory is altered, by comparing the calculated signature and the decrypted signature.

8. The information processing apparatus according to claim 7, wherein the signature is a hash value of the program.

9. An information processing apparatus comprising:

a memory storing a program;

a system bus;

a clock control unit configured to control a frequency of a clock to be supplied to read data via the system bus;

a clock supply unit configured to supply the clock having the frequency controlled by the clock control unit;

a first control unit configured to read the program stored in the memory via the system bus and to verify the read program; and

a second control unit configured to read the program judged as not being altered by the verification, from the memory via the system bus and to execute the read program,

wherein the clock control unit controls the frequency of the clock to be supplied by the clock supply unit to read the data via the system bus in such a manner that the frequency of the clock to be supplied by the clock supply unit to read the data via the system bus, from at least a time point at which the first control unit starts reading the program via the system bus to a time point at which the reading is finished, is higher than the frequency of the clock to be supplied by the clock supply unit to read the data via the system bus after the program is judged as not being altered by the verification.

10. A method of controlling an information processing apparatus including a memory storing a program,

a system bus,

a first control unit configured to read the program stored in the memory via the system bus and judge whether the read program is altered, and

a second control unit configured to read the program judged as not being altered from the memory via the system bus and execute the program,

the method comprising:

supplying a clock to the system bus and a clock to the first control unit,

wherein the supplying includes controlling a frequency of the clock to be supplied to the system bus and a frequency of the clock to be supplied to the first control unit in such a manner that the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit, from a time point at which the first control unit starts reading the program to at least a time point at which the reading is finished, are higher than the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit, respectively, after the judgement about the program.

11. The method according to claim 10, wherein the controlling controls the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit in such a manner that the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit, from the time point at which the first control unit starts reading the program to at least the time point at which the reading is finished, are higher than the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit, respectively, after the judgement about the program.

12. The method according to claim 10, wherein the frequency of the clock to be supplied to the system bus and the frequency of the clock to be supplied to the first control unit are different.

13. The method according to claim 12, wherein the frequency of the clock to be supplied to the system bus is higher than the frequency of the clock to be supplied to the first control unit.

14. The method according to claim 10,

wherein the information processing apparatus further includes a clock supply unit configured to generate the clock to be supplied to the system bus and the clock to be supplied to the first control unit, and

wherein the controlling sets the frequencies of the clocks to be supplied to the clock supply unit, and controls the frequencies.

15. The method according to claim 10, further comprising controlling supply of power to the first control unit and the second control unit,

wherein the controlling supplies power to the first control unit and does not supply power to the second control unit from the time point at which the first control unit starts reading the program to a time point at which the judgement is finished, and after the judgement is finished, the controlling supplies power to the first control unit and the second control unit.

16. The method according to claim 10,

wherein the memory stores a signature of the program that is encrypted with a private key,

wherein the judgement by the first control unit includes

calculating a signature of the program read from the memory via the system bus,

reading the encrypted signature from the memory, and

decrypting the read encrypted signature with a public key, and

wherein the first control unit judges whether the program stored in the memory is altered, by comparing the calculated signature and the decrypted signature.

17. The method according to claim 16, wherein the signature is a hash value of the program.