PHYSICAL AND LOGICAL ATTACK RESILIENT POLYMORPHIC HARDWARE

• US 20200134235A1
• Filed: 10/31/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Application

• Current Assignee: Kameleonsec Ltd.
• Original Assignee: Kameleonsec Ltd.
• Inventors: SASSON, Efi, MYSZNE, Jorge, TANNE, Ronen
• Application Number:
  US16/670,110
• Publication Number:
  US 20200134235A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/566 Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2221/2125 Just-in-time application of countermeasures, e.g., on-the-fly decryption, just-in-time obfuscation or de-obfuscation
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 63/1441 Countermeasures against malicious traffic countermeasures against attacks on cryptographic mechanisms H04L9/002
• CPC Class Codes: H04L 63/1491 using deception as countermeasure, e.g. honeypots, honeynets, decoys or entrapment
• CPC Class Codes: H04L 63/20 for managing network security; network security policies in general filtering policies H04L63/0227
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees

Abstract

An attack resilient distributed proactive polymorphic hardware, the including: at least one polymorphic core including at least one polymorphic logic, the at least one polymorphic logic adapted to adjust an implementation of a proactive polymorphic model without changing the contextual functionality of the proactive polymorphic model; a framework list defining at least one policy to be executed by the proactive polymorphic model; and a graph designating a historical description of each of the at least one policy executed by the proactive polymorphic model.

Claims

1. An attack resilient distributed proactive polymorphic hardware, comprising:

at least one polymorphic core including at least one polymorphic logic, the at least one polymorphic logic adapted to adjust an implementation of a proactive polymorphic model without changing the contextual functionality of the proactive polymorphic model;

a framework list defining at least one policy to be executed by the proactive polymorphic model; and

a graph designating a historical description of each of the at least one policy executed by the proactive polymorphic model.

2. The proactive polymorphic hardware of claim 1, wherein the at least one polymorphic core adjusts an implementation of the proactive polymorphic model by at least one of:

configuring the proactive polymorphic model and training the proactive polymorphic model.

3. The proactive polymorphic hardware of claim 1, wherein the implementation of the proactive polymorphic model includes executing the at least one policy of the proactive polymorphic hardware based on a decision mechanism and at least one of:

a neuron and a gate.

4. The proactive polymorphic hardware of claim 3, wherein the decision mechanism is based on a finite state machine (FSM), and wherein a neuron is included within a polymorphic core.

5. The proactive polymorphic hardware of claim 4, wherein the neuron is based on trainable logics, including as least one of:

a perceptron, a weighted trainable logic, a logical configuration, and an FSM based trainable mechanism.

6. The proactive polymorphic hardware of claim 1, wherein any subsequent policy selection by the proactive polymorphic hardware is based on previously selected policies which are described and stored in the graph.

7. The proactive polymorphic hardware of claim 1, wherein the framework list includes at least one of:

a framework for generation of a finite state machine (FSM), a majority vote mechanism, an authenticator, one or more traps, an activation module, and a unique identification.

8. The proactive polymorphic hardware of claim 7, wherein the traps include at least one of:

a honeypot, a canary logic, and a hooking logic.

9. The proactive polymorphic hardware of claim 8, wherein the majority vote policy is a policy determining a predetermined majority vote threshold of the at least one polymorphic core, wherein the predetermined majority vote threshold is required for execution of a policy by the proactive polymorphic hardware.

10. The proactive polymorphic hardware of claim 1, wherein the proactive polymorphic hardware further comprises:

a self-trusted distributed polymorphic fabric, wherein the trusted distributed polymorphic fabric is configured to provide a secure interface between the at least one polymorphic core, the framework list, and the graph.

11. The proactive polymorphic hardware of claim 1, wherein the proactive polymorphic hardware is further connected to a distributed network, wherein the distributed network includes additional proactive polymorphic hardware.

12. The proactive polymorphic hardware of claim 1, wherein the distributed network is a distributed ledger.

13. The proactive polymorphic hardware of claim 1, further comprising:

adapting a binary of a selected policy, software, or both, to a current architecture of the proactive polymorphic model to produce an output, wherein the output is agnostic to the current architecture of the proactive polymorphic model.

14. A polymorphic core, comprising:

at least one hardware logic configured to execute specific functions of a proactive polymorphic model; and

a polymorphic logic, wherein the polymorphic logic includes a decision mechanism and at least one neuron.

15. The proactive polymorphic hardware of claim 14, wherein the decision mechanism is based on a finite state machine (FSM), and wherein the neuron is based on trainable logics, including as least one of:

a perceptron, a weighted trainable logic, a logical configuration, and an FSM based trainable mechanism.

16. The proactive polymorphic hardware of claim 15, wherein the at least one hardware logic includes at least one of:

a framework list read logic, a graph update logic, a majority vote logic, and a policy choice logic.

17. The proactive polymorphic hardware of claim 15, wherein the at least one hardware logic has a polymorphic structure.

18. The proactive polymorphic hardware of claim 14, wherein the polymorphic logic is configured to create polymorphic software to be executed either on a polymorphic logic or on a discrete deterministic logic.

19. A method of establishing a topology of a proactive polymorphic model, comprising:

activating an application topology for a proactive polymorphic model, wherein the application topology is based on an infrastructure topology of the application topology;

activating a security topology of a proactive polymorphic model, wherein the security topology is based on an infrastructure topology.

20. The method of claim 19, further comprising:

determining if a previous topology for the proactive polymorphic model exists;

authentication the previous topology; and

polymorphing the proactive polymorphic model with a new security topology.

21. The method of claim 19, wherein each of the infrastructure topology, application topology, and security topology are determined based on a majority vote.