FLIP-FLOP BASED TRUE RANDOM NUMBER GENERATOR (TRNG) STRUCTURE AND COMPILER FOR SAME

• US 20200134249A1
• Filed: 12/26/2019
• Published: 04/30/2020
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: ZHOU, Charlie, HUANG, Tze-Chiang, LIU, Jack
• Granted Patent: US 11,568,116 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2207/583 Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes

Abstract

A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

Claims

1. A computer system for generating a model of a flip-flop chain, the computer system comprising:

a memory that stores a compiler; and

a processor configured to execute the compiler, the compiler, when executed by the processor configuring the processor to;

receive one or more first standard cells corresponding to a flip-flop and one or more second standard cells corresponding to a complement of the flip-flop;

receive one or more third standard cells corresponding to logic circuitry; and

interconnect the one or more first standard cells, the one or more second standard cells, and the one or more third standard cells in accordance with a polynomial to generate the model of the flip-flop chain.

2. The computer system of claim 1, wherein the one or more first standard cells comprise:

a model of the flip-flop in a software language, and

wherein the one or more second standard cells comprise;

a model of the complement of the flip-flop in the software language.

3. The computer system of claim 1, wherein the compiler, when executed by the processor, configures the processor to:

receive an equivalent number of the one or more first standard cells and the one or more second standard cells.

4. The computer system of claim 1, wherein the compiler, when executed by the processor, configures the processor to:

interconnect the one or more first standard cells, the one or more second standard cells, and the one or more third standard cells in accordance with one or more coefficients of the polynomial.

5. The computer system of claim 4, wherein the compiler, when executed by the processor, configures the processor to:

couple the one or more first standard cells and the one or more second standard cells to generate the flip-flop chain, and

couple a plurality signal pathways between the flip-flop chain and the one or more third standard cells corresponding to the logic circuitry in accordance with the plurality coefficients of the polynomial to generate the software model of the flip-flop chain.

6. The computer system of claim 5, wherein the compiler, when executed by the processor, configures the processor to:

couple a signal pathway from among the plurality of signal pathways to the one or more third standard cells corresponding to the logic circuitry when its corresponding coefficient from among the plurality coefficients is a one; and

not couple the signal pathway to the one or more third standard cells corresponding to the logic circuitry when its corresponding coefficient from among the plurality coefficients is a zero.

7. The computer system of claim 1, wherein the compiler, when executed by the processor further configures the processor to:

import the software model of the flip-flop chain into a library of standard cells as one or more fourth standard cells.

8. A flip-flop chain, comprising:

a plurality of flip-flops configured to provide a plurality of logical numbers in accordance with a plurality of degrees of a polynomial, each flip-flop from among the plurality of flip-flops corresponding to a degree from among the plurality of degrees and a coefficient from among a plurality of coefficients of the polynomial; and

first logic circuitry configured to perform one or more logical operations on a digital input and logical numbers from among the plurality of logical numbers corresponding to flip-flops from among the flip-flops whose coefficients from among the plurality of coefficients are ones to provide a digital output to the plurality of flip-flops.

9. The chain of claim 8, wherein a first flip-flop from among the plurality of flip-flops comprises:

first flip-flop circuitry configured to sense one or more statistically entropy noise signals corresponding to one or more microscopic phenomena to provide a first output bit;

second logic circuitry configured to perform one or more first logical operations on the first output bit in accordance with the digital output to provide a first output sequence of bits; and

second flip-flop circuitry configured to re-time the first output sequence of bits in accordance with a clocking signal to provide a first number from among the plurality of logical numbers.

10. The chain of claim 9, wherein the first flip-flop circuitry is configured to adjust a bias of the first output bit to be, on average, a similar number of logical ones and logical zeros over a given duration of time.

11. The chain of claim 9, wherein the first flip-flop circuitry corresponds to a least significant degree from among the plurality of degrees of the polynomial.

12. The chain of claim 9, wherein a second flip-flop from among the plurality of flip-flops comprises:

third flip-flop circuitry configured to sense the one or more statistically entropy noise signals corresponding to the one or more microscopic phenomena to provide a second output bit;

third logic circuitry configured to perform one or more second logical operations on the second output bit in accordance with the first number to provide a second output sequence of bits; and

fourth flip-flop circuitry configured to re-time the second output sequence of bits in accordance with the clocking signal to provide a second number from among the plurality of logical numbers.

13. The chain of claim 8, wherein a number of flip-flops of the plurality of flip-flops corresponds to a number of degrees of the plurality of degrees of the polynomial.

14. The chain of claim 8, wherein at least one flip-flop from among the plurality of flip-flops is a complement of a second flip-flop from among the plurality of flip-flops.

15. The chain of claim 8, wherein the first logic circuitry is further configured to not perform the one or more logical operations on logical numbers from among the plurality of logical numbers corresponding to flip-flops from among the flip-flops whose coefficients from among the plurality of coefficients are zeros.

16. A flip-flop chain, comprising:

a plurality of chains configured to provide a plurality of logical numbers in accordance a plurality of polynomials, each chain from among the plurality of chains comprising;

a plurality of flip-flops configured to provide a corresponding set of logical numbers from among the plurality of logical numbers in accordance with a plurality of degrees of a corresponding polynomial from among the plurality of polynomials, each flip-flop from among the plurality of flip-flops corresponding to a degree from among the plurality of degrees and a coefficient from among a plurality of coefficients of the corresponding polynomial, and

first logic circuitry configured to perform one or more logical operations on a digital input and logical numbers from among the corresponding set of logical numbers corresponding to flip-flops from among the flip-flops whose coefficients from among the plurality of coefficients are ones to provide a digital output to the plurality of flip-flops.

17. The chain of claim 16, wherein the plurality of polynomials are similar polynomials.

18. The chain of claim 16, wherein a first flip-flop from among the plurality of flip-flops comprises:

first flip-flop circuitry configured to sense one or more statistically entropy noise signals corresponding to one or more microscopic phenomena to provide a first output bit;

second logic circuitry configured to perform one or more first logical operations on the first output bit in accordance with the digital output to provide a first output sequence of bits; and

second flip-flop circuitry configured to re-time the first output sequence of bits in accordance with a clocking signal to provide a first number from among the plurality of logical numbers.

19. The chain of claim 18, wherein a second flip-flop from among the plurality of flip-flops comprises:

third flip-flop circuitry configured to sense the one or more statistically entropy noise signals corresponding to the one or more microscopic phenomena to provide a second output bit;

third logic circuitry configured to perform one or more second logical operations on the second output bit in accordance with the first number to provide a second output sequence of bits; and

fourth flip-flop circuitry configured to re-time the second output sequence of bits in accordance with the clocking signal to provide a second number from among the plurality of logical numbers.

20. The chain of claim 16, wherein the first logic circuitry is further configured to not perform the one or more logical operations on logical numbers from among the plurality of logical numbers corresponding to flip-flops from among the flip-flops whose coefficients from among the plurality of coefficients are zeros.