Method and Structure for Mandrel and Spacer Patterning

• US 20200134250A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 07/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chung-Ming, Peng, Chih-Hsiung, Chang, Chi-Kang, Chen, Kuei-Shun, Fu, Shih-Chi
• Granted Patent: US 11,010,526 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region

Abstract

A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Claims

1. A semiconductor device, comprising:

a first active fin on a substrate;

a second active fin on the substrate and separate from the first active fin; and

a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the first fin stub is lower than both the first and second active fins in height,

wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

2. The semiconductor device of claim 1, wherein the second active fin is oriented lengthwise in the first direction.

3. The semiconductor device of claim 1, wherein the first direction and the second direction form an angle no more than 30 degrees.

4. The semiconductor device of claim 1, further comprising:

a third active fin on the substrate and substantially parallel to the second active fin; and

a second fin stub on the substrate, wherein the second fin stub connects the first end of the first active fin and a first end of the third active fin, wherein the second fin stub is lower than both the first and third active fins in height.

5. The semiconductor device of claim 4, wherein from the top view the second fin stub is oriented lengthwise in a third direction that is different from either the first direction or the second direction.

6. The semiconductor device of claim 4, further comprising:

a fourth active fin on the substrate and substantially parallel to the second active fin, wherein the fourth active fin is disposed between the second and third active fins.

7. The semiconductor device of claim 1, further comprising:

an isolation feature over the first fin stub and between the first and second active fins, wherein the isolation feature is higher than the first fin stub and lower than both the first and second active fins in height.

8. The semiconductor device of claim 1, further comprising:

a third active fin on the substrate and substantially parallel to the first active fin; and

a second fin stub on the substrate, wherein the second fin stub connects a second end of the first active fin with a second end of the third active fin, wherein the second fin stub is lower than both the first and third active fins.

9. The semiconductor device of claim 8, wherein the second fin stub is oriented lengthwise in a third direction that is substantially perpendicular to the first direction.

10. A semiconductor device, comprising:

first, second, and third active fins on a substrate and separate from each other;

a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin;

a second fin stub on the substrate, wherein the second fin stub connects the bottom portion of the first active fin and a bottom portion of the third active fin; and

an isolation feature over the first and the second fin stubs, wherein the isolation feature is higher than the first and the second fin stubs and lower than the first, second, and third active fins, wherein from a top view the first, second, and third active fins are oriented lengthwise in a first direction, the first fin stub is oriented lengthwise in a second direction that is different from the first direction, and the second fin stub is oriented lengthwise in a third direction that is different from the first and second directions.

11. The semiconductor device of claim 10, wherein the first direction and the second direction form an angle not more than 30 degrees.

12. The semiconductor device of claim 10, wherein a width of the first active fin is larger than that of either the second active fin or the third active fin.

13. The semiconductor device of claim 10, wherein the second active fin is spaced from the third active fin with a first fin pitch, further comprising:

a fourth active fin oriented lengthwise in the first direction, wherein the fourth active fin is spaced from the first active fin with a second fin pitch, and wherein the second fin pitch is larger than the first fin pitch.

14. The semiconductor device of claim 13, further comprising:

a fifth active fin oriented lengthwise in the first direction, wherein the fifth active fin is spaced from the third active fin with the first fin pitch; and

a third fin stub on the substrate, wherein the third fin stub connects a bottom portion of the fourth active fin and a bottom portion of the fifth active fin, and wherein the isolation feature is higher than the third fin stub and lower than both the fourth and the fifth active fins.

15. The semiconductor device of claim 10, wherein the isolation feature includes silicon oxide, and wherein the first, second, and third active fins and the first and second fin stubs include silicon.

16. A semiconductor device, comprising:

a first active fin on a substrate and extending lengthwise in a first direction, the first active fin having a first end and a second end;

a first fin stub on the substrate and physically contacting a bottom portion of the first end of the first active fin, the first fin stub extending lengthwise in a second direction different from the first direction; and

a second fin stub on the substrate and physically contacting a bottom portion of the second end of the first active fin, the second fin stub extending lengthwise in a third direction different from either the first or the second directions,

wherein the first active fin is higher than both the first and second fin stubs in height.

17. The semiconductor device of claim 16, wherein:

the first direction and the second direction form an angle no more than 45 degrees; and

the third direction is substantially perpendicular to the first direction.

18. The semiconductor device of claim 16, further comprising:

a second active fin on the substrate, wherein the first fin stub physically contacting a bottom portion of the second active fin; and

a third active fin on the substrate, wherein the second fin stub physically contacting a bottom portion of the third active fin.

19. The semiconductor device of claim 18, wherein each of the second and third active fins extends lengthwise in the first direction.

20. The semiconductor device of claim 16, further comprising:

an isolation feature over the substrate and covering the first and second fin stubs, wherein the isolation feature is higher than the first and second fin stubs and lower than the first active fin in height.