MIXED SIGNAL COMPUTER ARCHITECTURE

• US 20200134268A1
• Filed: 04/16/2018
• Published: 04/30/2020
• Est. Priority Date: 04/17/2017
• Status: Active Grant

• Current Assignee: Octavo Systems LLC
• Original Assignee: Octavo Systems LLC
• Inventors: Frantz, Gene Alan
• Granted Patent: US 11,308,290 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G06J 3/00 Systems for conjoint operation of complete digital and complete analogue computers
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G16H 40/60 for the operation of medical equipment or devices
• CPC Class Codes: H03M 1/02 Reversible analogue/digital converters
• CPC Class Codes: H03M 1/18 Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

Abstract

The present disclosure describes a computer using a combination of analogue and digital components/elements used in a cohesive manner. Depending on the signals and data the computer manipulates, the analog processing elements and digital processing elements can be used separately, independently or in combination to optimize the computational results and the performance of the computer.

Claims

1-3. -3. (canceled)

4. A mixed signal computer, comprising:

one or more digital ALUs;

one or more digital registers, wherein at least one of said digital registers is connected to least one of said digital ALUs;

one or more analog ALUs;

one or more analog registers, wherein at least one of said analog registers is connected to least one of said analog ALUs; and

one or more exchange registers, wherein said exchange registers are interconnected with at least one of said digital registers and at least one of said analog registers.

5. The mixed signal computer of claim 4, further comprising:

a control unit, wherein said control unit is configured to control said one or more digital ALUs, said one or more analog ALUs, and said one or more exchange registers.

6. The mixed signal computer of claim 5, further comprising:

a digital memory; and

an analog memory.

7. The mixed signal computer of claim 6, further comprising:

a plurality of inputs, wherein at least one of said inputs is analog and at least one of said inputs is digital; and

a plurality of outputs, wherein at least one of said outputs is analog and at least one of said outputs is digital.

9. The mixed signal computer of claim 5, wherein said one or more analog ALUs operate continuously responsive to a set of instructions from the control unit using a clock signal independent of the clock signal operating said one or more digital ALUs.

11. The mixed signal computer of claim 6, further comprising:

an automatic gain control circuit controlled by said control unit to scale data values stored in said analog memory; and

a data shifter controlled by said control unit to scale data values stored in said digital memory.

12. The mixed signal computer of claim 6, wherein:

a mantissa of a data value is stored in said analog memory, and

an exponent for said mantissa of a stored value is stored in said digital memory.

14. The mixed signal computer of claim 6, wherein said control unit is configured such that analog data words are written into both said analog and said digital memories using the same address location, and

wherein data written into said analog memory is converted to a digital format and stored at the corresponding address location in said digital format in said digital memory.

16. The mixed signal computer of claim 14, wherein a flag is set in a register indicating said conversion.

17. The mixed signal computer of claim 6, wherein said control unit is configured such that digital data words are written into both said analog and said digital memories using the same address location for the corresponding memory array, wherein data written into said digital memory is converted to an analog format and stored at the corresponding address location in said analog format in said analog memory.

18. The mixed signal computer of claim 17, wherein a flag is set in a register indicating said conversion.

20. The mixed signal computer of claim 5, wherein said analog and digital ALUs are selectively synchronized based on at least one of the following:

a sample clock, an instruction from said control unit, or an interrupt.

22. The mixed signal computer of claim 6, wherein a set of registers are employed to identify when one or more of an analog memory location is refreshed based on its digital counterpart, a digital memory location is refreshed based on its analog counterpart, a digital memory location is refreshed based on an equivalent memory update, and an analog memory location is directly refreshed.

23. The mixed signal computer of claim 5, wherein said digital ALU is provided with intermediate results from said analog ALU, based on at least one of the following:

a predetermined instruction from said control unit, a clock set up by said control unit, and a predetermined interrupt set up by said control unit.

24. The mixed signal computer of claim 5, wherein said analog ALU is provided with intermediate results from said digital ALU, responsive to a predetermined instruction from said control unit.

38. The mixed signal computer of claim 6, wherein each analog ALU comprises:

one or more analog registers, and

wherein each analog ALU is configured to perform at least one arithmetic operation and at least one logic operation.

39. The mixed signal computer of claim 38, wherein said logic operations comprise:

a greater than operation and a less than operation,

a load operation and a store operation, and

at least one of an Or, And, Exclusive Or, Nor, Nand, or Invert operation.

8. (canceled)

10. (canceled)

13. (canceled)

15. (canceled)

19. (canceled)

21. (canceled)

25. (canceled)

26. An exchange register, comprising:

a digital register with two or more bits connected to a digital ALU;

an analog register connected to an analog ALU;

an analog to digital converter connected to said analog and digital registers;

a digital to analog converter connected to said digital and analog registers;

an automatic gain control circuit to scale data in said analog register;

a data shifter circuit to scale data in said digital register; and

a controller.

27. The exchange register of claim 26, further comprising:

a memory, wherein said controller is configured to manage the exchange register based on instructions or commands stored in said memory.

28-36. -36. (canceled)

37. A method for performing floating point operations using a mixed signal computer, comprising:

reading a first floating point value and a second floating point value from a digital and analog memory of said mixed signal processor using a digital ALU and an analog ALU of said mixed signal processor, wherein the first floating point value comprises a first mantissa and a first exponent and the second floating point value comprises a second mantissa and a second exponent, the first and second mantissa stored in an analog format in the analog memory and the first and second exponent stored in a digital format in the digital memory;

processing said first and second floating point value using said digital ALU and analog ALU to create a new floating point value comprising a third mantissa and a third exponent based on said processing; and

storing said new floating point value in registers associated with said digital and analog ALUs, wherein the third mantissa is stored in the analog format in the analog memory and the third exponent is stored in the digital format in the digital memory.