SYSTEM-ON-A-CHIP INCORPORATING ARTIFICIAL NEURAL NETWORK AND GENERAL-PURPOSE PROCESSOR CIRCUITRY

• US 20200134416A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Corelis Incorporated (Electronic Warfare Associates Incorporated)
• Original Assignee: Electronic Warfare Associates Incorporated
• Inventors: Niggemeyer, Dirk, Foster, Lester A., Rudnick, Elizabeth M.
• Granted Patent: US 11,580,355 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 18/22 Matching criteria, e.g. proximity measures
• CPC Class Codes: G06F 18/2413 based on distances to training or reference patterns
• CPC Class Codes: G06F 18/2431 Multiple classes
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G06V 10/764 using classification, e.g. of video objects
• CPC Class Codes: G06V 10/82 using neural networks
• CPC Class Codes: G06V 10/95 structured as a network, e.g. client-server architectures
• CPC Class Codes: G10L 15/02 Feature extraction for speech recognition; Selection of recognition unit
• CPC Class Codes: G10L 15/16 using artificial neural networks
• CPC Class Codes: G10L 2015/025 Phonemes, fenemes or fenones being the recognition units
• CPC Class Codes: G10L 25/51 : for comparison or discrimination
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit system and a method of analyzing audio or video input data that is capable of detecting, classifying, and post-processing patterns in an input data stream. The circuit system may consist of one or more digital processors, one or more configurable spiking neural network circuits, and digital logic for the selection of two-dimensional input data. The system may use the neural network circuits for detecting and classifying patterns and one or more the digital processors to perform further detailed analyses on the input data and for signaling the result of an analysis to outputs of the system.

Claims

1. A method of processing data comprising:

with at least one neural network circuit, detecting at least one characteristic of the data with at least one portion of at least one processor circuit in a lower power or no power state, wherein the lower power state corresponds to a state in which less power is consumed by the least one portion of the at least one processor circuit than is specified for its nominal operating state; and

in response to the detecting, powering the at least one processor circuit to perform processing on the data.

2. The method of claim 1, wherein the detecting includes 2-dimensional pattern matching.

3. The method of claim 1, wherein the processing includes image detection and image classification.

4. The method of claim 1, wherein the processing includes spectral analysis to identify emitters.

5. The method of claim 1, wherein the processing includes convolution processing.

6. The method of claim 1, wherein the processing includes identifying those speaking or spoken phenomes.

7. The method of claim 1, wherein the processing includes identifying acoustic signatures of physical phenomena.

8. The method of claim 2, further comprising programming weights in the at least one neural network circuit to determine a set of patterns to be detected.

9. The method of claim 2, wherein the detecting includes classifying the data into a number of images and/or pattern classes.

10. The method of claim 1, further comprising converting the data into analog signals and applying the analog signals to the at least one neural network circuit.

11. The method of claim 1, further comprising converting analog output of the at least one neural network circuit to digital signals and applying the digital signals to the at least one processor circuit.

12. The method of claim 1, wherein the detecting includes evaluating the data to find at least one object or at least one signature, or both, of interest.

13. The method of claim 1, wherein the processing includes detecting and classifying at least one object or at least one signature, or both, of interest.

14. The method of claim 1, wherein the at least one neural network circuit and the at least one processor circuit consume less than 1 mW in the lower power or no power state.

15. The method of claim 1, further comprising programming a functionality of the at least one neural network circuit using programmable storage elements.

16. The method of claim 15, further comprising calculating a set of weights on external compute equipment and programming the set of weights into the programmable storage elements.

17. A data processing system, comprising:

at least one neural network circuit constructed and arranged to receive data and detect at least one characteristic of the data; and

at least one processor circuit constructed and adapted into a lower power or no power state until the at least one neural network circuit detects the at least one characteristic and then adapted into a powered state to perform processing on the data, wherein the lower power state corresponds to a state in which less power is consumed by the at least one processor circuit than is specified for its nominal operating state.

18. The system of claim 17, wherein the at least one neural network circuit and the at least one processor circuit are on a single chip.

19. The system of claim 17, further comprising a buffer circuit constructed and arranged to receive the data and output the data to the at least one neural network circuit and the at least one processor circuit.

20. The system of claim 17, further comprising a data selection circuit constructed and arranged to receive the data and provide portions of the data to the at least one numerical control circuit.

21. The system of claim 20, wherein the at least one processor controls the data selection circuit.

22. The system of claim 17, further comprising a digital-to-analog circuit constructed and arranged to convert the data to analog data and apply the analog data to the at least one neural network circuit.

23. The system of claim 17, further comprising an analog-to-digital circuit constructed and adapted to convert an analog output of the at least one numerical control circuit to a digital signal and apply the digital signal to the at least one processor circuit.