ARITHMETIC PROCESSING DEVICE, LEARNING PROGRAM, AND LEARNING METHOD
First Claim
1. An arithmetic processing device comprising:
- an arithmetic circuit;
a register which stores operation output data that is output by the arithmetic circuit;
a statistics acquisition circuit which generates, from subject data that is either the operation output data or normalization subject data, a bit pattern indicating a position of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data; and
a statistics aggregation circuit which generates either positive statistical information or negative statistical information, or both positive and negative statistical information, by separately adding up a first number at respective bit positions of the leftmost set bit indicated by the bit pattern of each of a plurality of subject data having a positive sign bit and a second number of at respective bit positions of leftmost zero bit indicated by the bit pattern of each of a plurality of subject data having a negative sign bit.
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Abstract
An arithmetic processing device includes an arithmetic circuit; a register storing operation output data; a statistics acquisition circuit generating, from subject data being either the operation output data or normalization subject data, a bit pattern indicating a position of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data, the leftmost bit being a bit different from a sign bit; and a statistics aggregation circuit generating either positive or negative statistical information, or both positive and negative statistical information, by separately adding up a first number at respective bit positions of the leftmost set bit indicated by the bit pattern of each of a plurality of subject data having a positive sign bit and a second number of at respective bit positions of the leftmost zero bit indicated by the bit pattern of each of a plurality of subject data having a negative sign bit.
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Citations
12 Claims
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1. An arithmetic processing device comprising:
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an arithmetic circuit; a register which stores operation output data that is output by the arithmetic circuit; a statistics acquisition circuit which generates, from subject data that is either the operation output data or normalization subject data, a bit pattern indicating a position of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data; and a statistics aggregation circuit which generates either positive statistical information or negative statistical information, or both positive and negative statistical information, by separately adding up a first number at respective bit positions of the leftmost set bit indicated by the bit pattern of each of a plurality of subject data having a positive sign bit and a second number of at respective bit positions of leftmost zero bit indicated by the bit pattern of each of a plurality of subject data having a negative sign bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A non-transitory computer-readable storage medium storing therein a learning program for causing a computer to execute a learning process in a deep neural network, the learning process comprising:
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reading, from a memory, statistical data of a histogram having, as a number of respective bins, a number at respective bit positions of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number within subject data that is either a plurality of operation output data output by an arithmetic circuit or a plurality of normalization subject data, calculating a mean value and a variance value of the subject data on the basis of the number of the respective bins, and approximate values each corresponding to the position of the leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data, and performing a normalization operation on the subject data on the basis of the mean value and the variance value.
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12. A learning method for causing a processor to execute a learning process in a deep neural network, the learning process comprising:
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reading, from a memory, statistical data of a histogram having, as a number of respective bins, a number at respective bit positions of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number within subject data that is either a plurality of operation output data output by an arithmetic circuit or normalization subject data, calculating a mean value and a variance value of the subject data on the basis of the number of the respective bins and approximate values each corresponding to the position of the leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data, and performing a normalization operation on the subject data on the basis of the mean value and the variance value.
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Specification