DYNAMIC RANGE AND LINEARITY OF RESISTIVE ELEMENTS FOR ANALOG COMPUTING

• US 20200134438A1
• Filed: 10/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Osborne, Randy, Zhang, Kevin Xiaoqiang
• Application Number:
  US16/600,888
• Publication Number:
  US 20200134438A1
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A resistive network include multiple resistive units; each resistive unit is made up of multiple resistive elements, which can be arranged in a parallel configuration. Each of the resistive elements can be programmable (e.g., switched on or off, or set to one of multiple resistance values). Furthermore, a method of analog computing includes configuring multiple resistive elements in each of multiple resistive units and configuring the resistive units into a network. The configuration of the resistive elements can be, for example, arranging them into a parallel combination. The method further includes programming each resistive unit, for example, by switching individual resistive elements into, or out of, the parallel combination.

Claims

1. An analog computer, comprising:

a first plurality of nodes;

a second plurality of nodes; and

a first plurality of resistive assemblies, each comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the first plurality of resistive elements being switched resistive elements,

at least a subset of the first plurality of nodes are connected to a common one of the second plurality of nodes via respective ones of the first plurality of resistive assemblies.

2. The analog computer of claim 1, wherein at least a subset of the second plurality of nodes are connected to a common one of the first plurality of nodes via respective ones of the first plurality of resistive assemblies.

3. The analog computer of claim 2, wherein each combination of a node in the first plurality of nodes and a node in the second plurality of node are interconnected via a respective one of the first plurality of resistive assemblies.

4. The analog computer of claim 1, wherein each of the switched resistive elements comprises a resistive device and a switching transistor connected in series with the resistive device.

5. The analog computer of claim 1, wherein each of the first plurality of resistive elements comprises a resistor.

6. The analog computer of claim 1, wherein each of the first plurality of resistive elements comprises a multilevel resistance device.

7. The analog computer of claim 6, wherein each of the multilevel resistance devices comprises a resistive random access memory (RRAM) element.

8. The analog computer of claim 1, further comprising:

a third plurality of nodes; and

a second plurality of resistive assemblies, each comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the plurality of resistive elements being switched resistive elements,

at least a subset of the second plurality of nodes are connected to a common one of the third plurality of nodes via respective ones of the second plurality of resistive assemblies.

9. The analog computer of claim 3, further comprising:

a third plurality of nodes; and

a second plurality of resistive assemblies, each comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the plurality of resistive elements being switched resistive elements,

wherein each combination of a node in the second plurality of nodes and a node in the third plurality of node are interconnected via a respective one of the second plurality of resistive assemblies.

10. The analog computer of claim 9, wherein:

each of the first plurality of resistive assemblies is configurable into;

a first configuration wherein a first subset of the plurality of resistive elements in each of the first plurality of resistive assemblies are adapted to be connected to each other in parallel;

a second figuration wherein a second subset of the plurality of resistive elements in each of the first plurality of resistive assemblies are adapted to be connected to each other in parallel; and

each of the second plurality of resistive assemblies is configurable into;

a first configuration wherein a first subset of the plurality of resistive elements in each of the second plurality of resistive assemblies are adapted to be connected to each other in parallel;

a second configuration wherein a second subset of the plurality of resistive elements in each of the second plurality of resistive assemblies are adapted to be connected to each other in parallel;

the analog computer being configurable into a plurality of mutually exclusive states in which;

in a first of the plurality of states, both the first and second pluralities of resistive assemblies are configured into the respective first configuration, and

in a second of the plurality of states, both the first and second pluralities of resistive assemblies are configured into the respective second configuration.

11. The analog computer of claim 1, wherein at least a second subset of the first plurality of nodes are connected to a second common one of the second plurality of nodes via respective ones of the plurality of resistive assemblies, the analog computer further comprising a differential amplifier adapted to receive a first output signal from the first common one of the second plurality of nodes and a second output signal from the second common one of the second plurality of nodes and to generate an output signal indicative of the difference between the first and second output signals.

12. The analog computer of claim 1, wherein each of the first plurality of nodes is adapted to receive a current signal, and the first plurality of the resistive assemblies are adapted to generate at each of the second plurality of nodes a respective weighted sum of the current signals received at the first plurality of nodes.

13. A method of computing, comprising:

receiving a first plurality of signals at a respective first plurality of nodes;

selecting at least one subset of a plurality of resistive elements in each of a first plurality of resistive assemblies;

for each of the first plurality of resistive assemblies, configuring the selected resistive elements into a parallel combination; and

transmitting at least one subset of the signals from a respective subset of the first plurality of nodes to a first one of a second plurality of nodes via the respective parallel combinations.

14. The method of claim 13, wherein the transmitting at least a subset of the signals comprises transmitting each of the at least one subset of the signals from each of a respective subset of the first plurality of nodes to each one of the second plurality of nodes via a respective one of the parallel combinations.

15. The method of claim 14, further comprising setting a resistance value of each of the at least one subset of a plurality of resistive elements in each of the first plurality of resistive assemblies to one of a plurality of resistance values.

16. The method of claim 14, further comprising:

selecting at least one subset of a plurality of resistive elements in each of a second plurality of resistive assemblies;

for each of the second plurality of resistive assemblies, configuring the selected resistive elements into a parallel combination; and

transmitting at least one subset of the signals from a respective subset of the second plurality of nodes to one of a third plurality of nodes via the respective parallel combinations.

17. The method of claim 16, further comprising:

setting resistance values of a first subset of resistive elements of each of the first plurality of resistive assemblies and a second subset of resistive element of the first plurality of resistive assemblies;

setting resistance values of a first subset of resistive elements of each of the second plurality of resistive assemblies and a second subset of resistive element of the second plurality of resistive assemblies;

wherein;

the transmitting at least one subset of the signals from the first to second plurality of nodes comprises, after the setting of the resistance values and without thereafter changing any of the set values, transmitting the signals via the first subset of resistive elements of each of the first plurality of resistive assemblies during a first time period and transmitting the signals via the second subset of resistive elements of each of the first plurality of resistive assemblies during a second time period; and

the transmitting at least one subset of the signals from the second to third plurality of nodes comprises, after the setting of the resistance values and without thereafter changing the values, transmitting the signals via the first subset of resistive elements of each of the second plurality of resistive assemblies during a second time period and transmitting the signals via the second subset of resistive elements of each of the second plurality of resistive assemblies during a second time period.

18. The method of claim 13, further comprising:

selecting at least one subset of a plurality of resistive elements in each of a second plurality of resistive assemblies;

for each of the second plurality of resistive assemblies, configuring the selected resistive elements into a parallel combination; and

transmitting the at least one subset of the signals from the respective subset of the first plurality of nodes to a second one of a second plurality of nodes via the respective parallel combinations;

the method further comprising generating a signal indicative of the difference between a combination of the signals transmitted to the first one of the second plurality of nodes and a combination of the signals transmitted to the second one of the second plurality of nodes.

19. An artificial neural network, comprising:

an upstream layer comprising a first plurality of nodes adapted to receive a respective plurality of signals;

a downstream layer comprising a second plurality of nodes; and

a plurality of resistance assemblies, each of which comprises a plurality of resistive elements in a parallel configuration, at least one of the resistive elements being a switched resistive element;

the switched resistive element in each resistive assembly comprising a resistive device and a switching device configured to connect the resistive device in parallel with the other resistive elements in the resistive assembly.

20. The artificial neural network of claim 19, wherein each of the switching devices comprises a control input adapted to receive a select-signal, the switching device adapted to connect the respective resistive device in parallel with the other resistive elements in the resistive assembly upon receiving the select-signal, each of the resistive elements comprising a multi-level resistance device.