IMAGE PROCESSING METHOD, CHIP, PROCESSOR, SYSTEM, AND MOBILE DEVICE

• US 20200134771A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 07/25/2017
• Status: Abandoned Application

• Current Assignee: SZ DJI Technology Co., Ltd. (d/b/a DJI) (iFlight Technology Company Limited)
• Original Assignee: SZ DJI Technology Co., Ltd. (d/b/a DJI) (iFlight Technology Company Limited)
• Inventors: XIE, Jin, GAO, Mingming, YANG, Kang
• Application Number:
  US16/728,832
• Publication Number:
  US 20200134771A1
• Time in Patent Office: Days
• CPC Class Codes: G06T 1/0007 Image acquisition
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 2200/28 involving image processing hardware

Abstract

An image processing method comprising acquiring a plurality of pixel rows of an image according to a rectangular pixel region, and storing the plurality of pixel rows as blocks in a plurality of line buffers. A pixel row is stored as a block in a storage space of the plurality of line buffers, and a number of bits of the block in a line buffer is smaller than a number of pixel columns of the image.

Claims

1. An image processing method comprising:

acquiring a plurality of pixel rows of an image according to a rectangular pixel region; and

storing the plurality of pixel rows as blocks in a plurality of line buffers,

wherein a pixel row is stored as a block in a storage space of the plurality of line buffers, and a number of bits of the block in a line buffer is smaller than a number of pixel columns of the image.

2. The image processing method of claim 1, wherein:

a number of the acquired pixel rows is not less than a difference between a number of pixel rows of the rectangular pixel region and a preset value.

3. The image processing method of claim 2, wherein:

the number of the acquired pixel rows is equal to the number of the pixel rows of the rectangular pixel region minus one.

4. The image processing method of claim 1, wherein:

the rectangular pixel region is a first rectangular pixel region,

a number of the blocks in one column of the plurality of line buffers is equal to a number of pixel rows of a second rectangular pixel region, wherein the number of the pixel rows of the second rectangular pixel region is smaller than the number of the pixel rows of the first rectangular pixel region.

5. The image processing method of claim 4, wherein:

the number of bits of the block in the line buffer is not less than a number of pixel columns of the second rectangular pixel region.

6. The image processing method of claim 4, wherein:

the first rectangular pixel region is a smallest rectangular pixel region for a pixel selection in a first algorithm of a plurality of algorithms,

the second rectangular pixel region is a smallest rectangular pixel region for a pixel selection in a second algorithm of the plurality of algorithms, and

the first rectangular pixel region covers the second rectangular pixel region.

7. The image processing method of claim 6, further comprising:

according to the second rectangular pixel region, reading pixels in corresponding line buffers of the plurality of line buffers, and selecting corresponding pixels to output to a second algorithm module.

8. The image processing method of claim 7, further comprising:

registering the read pixels into a register; and

according to the first rectangular pixel region, splicing multi-registered pixels in the register and selecting corresponding pixels to output to a first algorithm module.

9. The image processing method of claim 6, wherein:

the first algorithm is Census algorithm, and the second algorithm is Harris algorithm.

10. The image processing method of claim 1, wherein:

the plurality of pixel rows are stored as blocks, in an order from top to bottom and from left to right in the storage space of the plurality of line buffers.

11. The image processing method of claim 1, wherein acquiring the plurality of pixel rows of the image according to the rectangular pixel region comprises:

acquiring the plurality of pixel rows by a first input first output (FIFO) manner.

12. A chip comprising:

a plurality of line buffers; and

a controller configured to;

acquire a plurality of pixel rows of an image according to a rectangular pixel region, and

store the plurality of pixel rows as blocks in the plurality of line buffers,

wherein a pixel row is stored as a block in a storage space of the plurality of line buffers, and a number of bits of the block in a line buffer is smaller than a number of pixel columns of the image.

13. The chip of claim 12, wherein:

a number of the acquired pixel rows is not less than a difference between a number of pixel rows of the rectangular pixel region and a preset value.

14. The chip of claim 12, wherein:

the rectangular pixel region is a first rectangular pixel region,

a number of the blocks in one column of the plurality of line buffers is equal to a number of pixel rows of a second rectangular pixel region, wherein the number of the pixel rows of the second rectangular pixel region is smaller than the number of the pixel rows of the first rectangular pixel region.

15. The chip of claim 14, wherein:

the number of bits of the block in the line buffer is not less than a number of pixel columns of the second rectangular pixel region.

16. The chip of claim 14, wherein:

the first rectangular pixel region is a smallest rectangular pixel region for a pixel selection in a first algorithm of a plurality of algorithms, and

the second rectangular pixel region is a smallest rectangular pixel region for a pixel selection in a second algorithm of the plurality of algorithms,

wherein the first rectangular pixel region covers the second rectangular pixel region.

17. The chip of claim 16, further comprising:

a second algorithm module,

wherein the controller is further configured to;

according to the second rectangular pixel region, read pixels in corresponding line buffers of the plurality of line buffers, and

selecting corresponding pixels to output to the second algorithm module.

18. The chip of claim 17, further comprising:

a register and a first algorithm module,

the controller is further configured to;

register the read pixels into the register;

according to the first rectangular pixel region, splice multi-registered pixels in the register; and

selecting corresponding pixels to output to the first algorithm module.

19. The chip of claim 16, wherein:

the first algorithm is Census algorithm, and the second algorithm is Harris algorithm.

20. A processor comprising:

a chip comprising a controller and a plurality of line buffers,

wherein the controller is configured to;

acquire a plurality of pixel rows of an image according to a rectangular pixel region, and

store the plurality of pixel rows as blocks in a plurality of line buffers,

wherein a pixel row is stored as a block in a storage space of the plurality of line buffers, and a number of bits of the block in a line buffer is smaller than a number of pixel columns of the image.