MECHANISM TO ACCELERATE GRAPHICS WORKLOADS IN A MULTI-CORE COMPUTING ARCHITECTURE

• US 20200134776A1
• Filed: 01/23/2019
• Published: 04/30/2020
• Est. Priority Date: 08/05/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Benthin, Carsten, Woop, Sven, Wald, Ingo
• Granted Patent: US 11,010,858 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Claims

1-20. -20. (canceled)

21. A processor comprising:

a plurality of processor cores, including;

a first processor core; and

a second processor core; and

a first field programmable gate array (FPGA) coupled to the first processor core to accelerate execution of workloads processed at the first processor core; and

a second FPGA coupled to the second processor core to accelerate execution of workloads processed at the second processor core.

22. The processor of claim 21, wherein the plurality of processor cores includes a general-purpose processor core.

23. The processor of claim 22, wherein the plurality of processor cores includes a graphics processor core.

24. The processor of claim 22, wherein the first processor core selects a first workload to be accelerated at the first FPGA and the second processor core selects a second workload to be accelerated at the second FPGA.

25. The processor of claim 22, wherein the first FPGA is programmed to execute a first type of workload and the second FPGA is programmed to execute a second type of workload.

26. The processor of claim 22, wherein the first and second FPGAs provide one or more independent threads to perform latency hiding.

27. The processor of claim 22, wherein the first processor core comprises a first controller to control execution of the first FPGA, and the second processor core comprises a second controller to control execution of the second FPGA.

28. The processor of claim 27, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via memory-mapped I/O (MMIO) regions.

29. The processor of claim 28, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via dedicated processor instructions.

30. The processor of claim 29, further comprising:

a first cache memory device coupled to the first processor core and the first FPGA; and

a second cache memory device coupled to the second processor core and the second FPGA.

31. The processor of claim 30, wherein the first FPGA is an independent agent to the first cache memory device, and the second FPGA is an independent agent to the second cache memory device.

32. The processor of claim 29, further comprising:

a third processor core coupled to the first FPGA; and

a first cache memory device coupled to the first processor core, the third processor core and the first FPGA, wherein the first FPGA accelerates execution of workloads processed at the first processor core and the third processor core.

33. The processor of claim 22, wherein the processor comprises a graphics processor unit (GPU).

34. The processor of claim 33, further comprising:

a first memory device coupled to the first processor core and the first FPGA; and

a second memory device coupled to the second processor core and the second FPGA.

35. The processor of claim 33, further comprising:

a third processor core coupled to the first FPGA; and

a first memory device coupled to the first processor core, the third processor core and the first FPGA, wherein the first FPGA accelerates execution of workloads processed at the first processor core and the third processor core.

36. A data processing system comprising:

a peripheral bus interconnect; and

a plurality of processor cores coupled with the peripheral bus interconnect, including;

a first processor core; and

a second processor core;

a first field programmable gate array (FPGA) coupled to the first processor core to accelerate execution of workloads processed at the first processor core;

a first cache memory device coupled to the first processor core and the first FPGA;

a second FPGA coupled to the second processor core to accelerate execution of workloads processed at the second processor core; and

a second cache memory device coupled to the second processor core and the second FPGA.

37. The data processing system of claim 36, wherein the first processor core selects a first workload to be accelerated at the first FPGA and the second processor core selects a second workload to be accelerated at the second FPGA.

38. The data processing system of claim 37, wherein the first FPGA is programmed to execute a first type of workload and the second FPGA is programmed to execute a second type of workload.

39. The data processing system of claim 38, wherein the first processor core comprises a first controller to control execution of the first FPGA, and the second processor core comprises a second controller to control execution of the second FPGA.

40. The data processing system of claim 36, further comprising a third processor core coupled to the first FPGA and the first cache memory device, wherein the first FPGA accelerates execution of workloads processed at the first processor core and the third processor core.