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TFT PIXEL THRESHOLD VOLTAGE COMPENSATION CIRCUIT WITH SHORT ONE HORIZONTAL TIME

  • US 20200135106A1
  • Filed: 10/26/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/26/2018
  • Status: Active Grant
First Claim
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1. A pixel circuit for a display device operable in a compensation phase, a data programming phase, and an emission phase, the pixel circuit comprising:

  • a drive transistor configured to control an amount of current to a light-emitting device during the emission phase depending upon a voltage input applied to a gate of the drive transistor;

    a second transistor and a third transistor, wherein the second transistor is directly connected between the gate of the drive transistor and the third transistor, and the third transistor is directly connected between the second transistor and a second terminal of the drive transistor, such that when the second and third transistors are in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are electrically connected through the second and third transistors, wherein a threshold voltage of the drive transistor is compensated during the compensation phase while the drive transistor is diode connected;

    wherein the light-emitting device is electrically connected at a first node to the second terminal of the drive transistor during the emission phase and at a second node to a first voltage input;

    a storage capacitor having a first plate connected to a third terminal of the drive transistor that receives a second voltage input, and a second plate connected to the gate of the drive transistor, anda programming capacitor having a first plate directly connected to the second and third transistors, and a second plate of the programming capacitor is electrically connected to a data voltage input during the data programming phase, wherein the first plate of the programming capacitor is electrically connected to the second plate of the storage capacitor when the second transistor is in an on state;

    wherein the second plate of the programming capacitor further is electrically connected to a reference voltage input to perform the compensation phase, and the programming capacitor further is electrically isolated from the storage capacitor and the drive transistor by the second and third transistors during the emission phase.

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