TFT PIXEL THRESHOLD VOLTAGE COMPENSATION CIRCUIT WITH SHORT ONE HORIZONTAL TIME

• US 20200135106A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Lu, Tong, Brownlow, Michael James
• Granted Patent: US 10,650,752 B1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A pixel circuit for a display device is operable in a compensation phase, a data programming phase, and an emission phase, whereby the one horizontal time is minimized while maintaining accurate compensation of the threshold voltage of the drive transistor. The pixel circuit includes: a storage capacitor having a first plate connected to a third terminal of the drive transistor that receives a voltage input, and a second plate connected to the gate of the drive transistor; and a programming capacitor having a first plate connected to second and third transistors, and a second plate of the programming capacitor is electrically connected to a data voltage input during the data programming phase, wherein the first plate of the programming capacitor is electrically connected to the second plate of the storage capacitor when the second transistor is in an on state. The second plate of the programming capacitor further is electrically connected to a reference voltage input to perform the compensation phase, and the programming capacitor further is electrically isolated from the storage capacitor and the drive transistor by the second and third transistors during the emission phase.

Claims

1. A pixel circuit for a display device operable in a compensation phase, a data programming phase, and an emission phase, the pixel circuit comprising:

a drive transistor configured to control an amount of current to a light-emitting device during the emission phase depending upon a voltage input applied to a gate of the drive transistor;

a second transistor and a third transistor, wherein the second transistor is directly connected between the gate of the drive transistor and the third transistor, and the third transistor is directly connected between the second transistor and a second terminal of the drive transistor, such that when the second and third transistors are in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are electrically connected through the second and third transistors, wherein a threshold voltage of the drive transistor is compensated during the compensation phase while the drive transistor is diode connected;

wherein the light-emitting device is electrically connected at a first node to the second terminal of the drive transistor during the emission phase and at a second node to a first voltage input;

a storage capacitor having a first plate connected to a third terminal of the drive transistor that receives a second voltage input, and a second plate connected to the gate of the drive transistor, and

a programming capacitor having a first plate directly connected to the second and third transistors, and a second plate of the programming capacitor is electrically connected to a data voltage input during the data programming phase, wherein the first plate of the programming capacitor is electrically connected to the second plate of the storage capacitor when the second transistor is in an on state;

wherein the second plate of the programming capacitor further is electrically connected to a reference voltage input to perform the compensation phase, and the programming capacitor further is electrically isolated from the storage capacitor and the drive transistor by the second and third transistors during the emission phase.

2. The pixel circuit of claim 1, further comprising a fourth transistor connected between the first node of the light-emitting device and an initialization voltage input, wherein the pixel circuit further is operable in an initialization phase during which the initialization voltage is applied to the light emitting device and to the gate of the drive transistor while diode connected.

3. The pixel circuit of claim 2, wherein the reference voltage input is the same as the initialization voltage input.

4. The pixel circuit of claim 1, wherein the reference voltage input is the same as the second voltage input applied to the third terminal of the drive transistor.

5. The pixel circuit of claim 1, further comprising a fifth transistor that is connected between the second terminal of the drive transistor and the first node of the light-emitting device, wherein the light-emitting device is electrically connected to the drive transistor through the fifth transistor during the emission phase and electrically isolated from the drive transistor during the compensation and data programming phases.

6. The pixel circuit of claim 1, further comprising a sixth transistor that is connected between the reference voltage input and the second plate of the programming capacitor.

7. The pixel circuit of claim 1, further comprising a seventh transistor that connected between the second plate of the programming capacitor and the data voltage input.

8. The pixel circuit of claim 1, further comprising a seventh transistor and an eighth transistor, wherein the seventh transistor is connected between the second plate of the programming capacitor and the eighth transistor, and the eighth transistor is connected between the seventh transistor and the data voltage input.

9. The pixel circuit of claim 7, further comprising the light-emitting device, wherein the light-emitting device is electrically connected to the drive transistor during the emission phase and electrically isolated from the drive transistor during the compensation and data programming phases.

10. The pixel circuit of claim 1, wherein the light-emitting device is one of an organic light-emitting diode, a micro light-emitting diode (LED), or a quantum dot LED.

11. The pixel circuit of claim 1, wherein the transistors are p-type transistors.

12. The pixel circuit of claim 1, wherein the transistors are n-type transistors.

13. A method of operating a pixel circuit for a display device comprising the steps of:

providing a pixel circuit comprising;

a drive transistor configured to control an amount of current to a light-emitting device during the emission phase depending upon a voltage input applied to a gate of the drive transistor;

a second transistor and a third transistor, wherein the second transistor is connected between the gate of the drive transistor and the third transistor, and the third transistor is connected between the second transistor and a second terminal of the drive transistor, such that when the second and third transistors are in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are electrically connected through the second and third transistors;

a storage capacitor having a first plate connected to a third terminal of the drive transistor that receives a second voltage input, and a second plate connected to the gate of the drive transistor, and

a programming capacitor having a first plate connected to the second and third transistors, and a second plate of the programming capacitor is electrically connectable to a data voltage input;

performing a compensation phase to compensate a threshold voltage of the drive transistor comprising diode-connecting the drive transistor through the second and third transistors and applying the reference voltage at the second plate of the programming capacitor while the drive transistor is diode connected, wherein the programming capacitor is isolated from the reference voltage at the end of the compensation phase;

performing a data programming phase to program the data voltage to the programming capacitor comprising applying the data voltage at a second plate of the programming capacitor while the second transistor is in an on state; and

performing an emission phase during which light is emitted from the light-emitting device comprising isolating the programming capacitor from the storage capacitor and the drive transistor, and applying the second voltage input through the drive transistor to the light emitting device.

14. The method of operating of claim 13, wherein the programming phase follows the threshold compensation phase.

15. The method of operating of claim 13, wherein a duration of the data programming phase is shorter than a duration of the compensation phase.

16. The method of operating of claim 13, further comprising performing an initialization phase comprising, prior to the compensation and data programming phases, applying an initialization voltage to a first node of the light emitting device and to the gate of the drive transistor via the diode-connection through the second and third transistors.

17. The method of operating of claim 16, wherein the reference voltage is the initialization voltage.

18. The method operating of claim 13, wherein the reference voltage is the second voltage input applied to the third terminal of the drive transistor.

19. The method of operating of claim 13, wherein the pixel circuit comprises two transistors connected between the data voltage input and the second plate of the programming capacitor, wherein during the data programming phase, SCAN signals from different rows of pixels respectively are applied to gates of the two transistors to apply the data voltage at the second plate of the programming capacitor.

20. The method of operating of claim 13, wherein the pixel circuit comprises a single transistor connected between the data voltage input and the second plate of the programming capacitor, wherein during the data programming phase, a dedicated SCAN signal is applied to a gate of the single transistor to apply the data voltage at the second plate of the programming capacitor.