DRIVE TECHNIQUES FOR MODULATION DEVICES

• US 20200135128A1
• Filed: 05/08/2018
• Published: 04/30/2020
• Est. Priority Date: 05/08/2017
• Status: Abandoned Application

• Current Assignee: Snap, Inc.
• Original Assignee: Compound Photonics Limited
• Inventors: FERGUSON, Kevin M.
• Application Number:
  US16/605,684
• Publication Number:
  US 20200135128A1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/002 to project the image of a two-dimensional display, such as an array of light emitting or modulating elements or a CRT
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2025 the sub-frames having all the same time duration
• CPC Class Codes: G09G 3/2029 the sub-frames having non-binary weights
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

One embodiment provides a driver controller for a light modulation device. The driver controller includes a look-up table (LUT) to store a plurality of binary sequences, each binary sequence corresponding to a target phase response of a pixel of a liquid crystal structure of the light modulation device; wherein at least one binary sequence includes at least one pattern of binary values from among a plurality of patterns of binary values, the patterns of binary values comprising: a first set of patterns, each pattern of the first set of patterns generated as: for n=N−1 . . . 1, n leading “0”s plus a trailing “1”; where n is an index ranging from 1 to N, and N represents a number of target phase responses; and a second set of patterns, each pattern of the second set of patterns generated as: for n=1 to N−2, generate pattern {01x}, where x=n number of trailing “1” s. The driver controller also includes pixel electrode control circuitry to receive data having N target phase responses for at least one pixel and to determine a binary sequence of the LUT that matches a target phase response of the data; the pixel electrode control circuitry also to cause a first voltage level, corresponding to a first binary value of a binary sequence, to be applied to an electrode of the pixel, and to cause a second voltage level, corresponding to a second binary value of a binary sequence, to be applied to the electrode of the pixel.

Claims

1. A driver controller for a light modulation device,

a look-up table (LUT) to store a plurality of binary sequences, each binary sequence corresponding to a target phase response of a pixel of a liquid crystal structure of the light modulation device;

wherein at least one binary sequence includes at least one pattern of binary values from among a plurality of patterns of binary values, the patterns of binary values comprising;

a first set of patterns, each pattern of the first set of patterns generated as;

for n=N−

1 . . . 1, n leading “

0”

s plus a trailing “

1”

;

where n is an index ranging from 1 to N, and N represents a number of target phase responses; and

a second set of patterns, each pattern of the second set of patterns generated as;

for n=1 to N−

2, generate pattern {01x}, where x=n number of trailing “

1”

s; and

pixel electrode control circuitry to receive data having N target phase responses for at least one pixel and to determine a binary sequence of the LUT that matches a target phase response of the data;

the pixel electrode control circuitry also to cause a first voltage level, corresponding to a first binary value of a binary sequence, to be applied to an electrode of the pixel, and to cause a second voltage level, corresponding to a second binary value of a binary sequence, to be applied to the electrode of the pixel.

2. The driver controller of claim 1, wherein the at least one binary sequence is represented as a repeating at least one pattern, from among the plurality of patterns, over a sample space;

wherein the sample space defines the maximum number of samples that are used for each sequence.

3. The driver controller of claim 1, wherein the patterns of binary values also include a pattern of repeating “

0”

s over a sample space and pattern of repeating “

1”

s over a sample space;

wherein the sample space defines the maximum number of samples that are used for each sequence.

4. The driver controller of claim 1, wherein each binary sequence of the LUT corresponds to a duty cycle, and wherein the LUT comprises a range of binary sequences representing a range of approximately linearly distributed duty cycles.

5. The driver controller of claim 4, wherein at least one sequence having binary values that have a maximum number of binary “

0”

s between each binary “

1”

for a duty cycle less than or equal to 50%.

6. The driver controller of claim 4, wherein at least one sequence having binary values that have a maximum number of binary “

1”

s between each binary “

0”

for a duty cycle greater than 50%.

7. The driver controller of claim 4, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate an approximately linearly distributed duty cycle;

wherein the sample space defines the maximum number of samples that are used for each sequence.

8. The driver controller of claim 1, wherein each of the patterns form a unique sequence, and each sequence representing a unique duty cycle and phase response, and wherein each sequence being tested to generate an actual phase response for each sequence and compared to a target phase response, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles corresponding to a first and second phase responses that are closest to the target phase response, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate sequence that approximately generates the target phase response.

9. The driver controller of claim 1, wherein the plurality of binary sequences representing a range of approximately linearly distributed phase responses.

10. The driver controller of claim 1, wherein the data comprises image data and the target phase response represents a bit depth level of the image data.

11. A method for generating a table of binary sequences to control a pixel of a light modulation device, comprising:

generating a first set of patterns, each pattern of the first set of patterns generated as;

for n=N−

1 . . . 1, n leading “

0”

s plus a trailing “

1”

;

where n is an index ranging from 1 to N, and N represents a number of target phase responses; and

generating a second set of patterns, each pattern of the second set of patterns generated as;

for n=1 to N−

2, generate pattern {01x}, where x=n number of trailing “

1”

s; and

determining, from among the first set of patterns and the second set of patterns, a pattern that matches a linearly distributed duty cycle and repeating that sample over a sample space being defined as the maximum number of samples that are used for each sequence; and

determining, from among the first set of patterns and the second set of patterns, a first pattern that is a closest match to a linearly distributed duty cycle and a second pattern that is a second closest match to the a linearly distributed duty cycle, and interpolating the first duty cycle and the second duty cycle and repeating the first and second pattern over the sample space.

12. The method of claim 11, wherein the patterns of binary values also include a pattern of repeating “

0”

s over the sample space and pattern of repeating “

1”

s over a sample space.

13. The method of claim 11, wherein each binary sequence of the LUT corresponds to a duty cycle, and wherein the LUT comprises a range of binary sequences representing a range of approximately linearly distributed duty cycles.

14. The method of claim 13, wherein at least one sequence having binary values that have a maximum number of binary “

0”

s between each binary “

1”

for a duty cycle less than or equal to 50%.

15. The method of claim 13, wherein at least one sequence having binary values that have a maximum number of binary “

1”

s between each binary “

0”

for a duty cycle greater than 50%.

16. The method of claim 11, wherein each of the patterns form a unique sequence, and each sequence representing a unique duty cycle and phase response, and wherein each sequence being tested to generate an actual phase response for each sequence and compared to a target phase response, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles corresponding to a first and second phase responses that are closest to the target phase response, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate sequence that approximately generates the target phase response.

17. The method of claim 11, wherein the plurality of binary sequences representing a range of approximately linearly distributed phase responses.

18. A light modulation system comprising:

a light modulation device having an array of liquid crystal pixels, each pixel being individually controllable; and

a driver controller to control the light modulation device, the driver controller comprising;

a look-up table (LUT) to store a plurality of binary sequences, each binary sequence corresponding to a target phase response of a pixel of the light modulation device;

wherein at least one binary sequence includes at least one pattern of binary values from among a plurality of patterns of binary values, the patterns of binary values comprising;

a first set of patterns, each pattern of the first set of patterns generated as;

for n=N−

1 . . . 1, n leading “

0”

s plus a trailing “

1”

;

where n is an index ranging from 1 to N, and N represents a number of target phase responses; and

a second set of patterns, each pattern of the second set of patterns generated as;

for n=1 to N−

2, generate pattern {01x}, where x=n number of trailing “

1”

s; and

pixel electrode control circuitry to receive data having N target phase responses for at least one pixel and to determine a binary sequence of the LUT that matches a target phase response of the data;

the pixel electrode control circuitry also to cause a first voltage level, corresponding to a first binary value of a binary sequence, to be applied to an electrode of the pixel, and to cause a second voltage level, corresponding to a second binary value of a binary sequence, to be applied to the electrode of the pixel.

19. The system of claim 18, wherein the at least one binary sequence is represented as a repeating at least one pattern, from among the plurality of patterns, over a sample space;

wherein the sample space defines the maximum number of samples that are used for each sequence.

20. The system of claim 18, wherein the patterns of binary values also include a pattern of repeating “

0”

s over a sample space and pattern of repeating “

1”

s over a sample space;

wherein the sample space defines the maximum number of samples that are used for each sequence.

21. The system of claim 18, wherein each binary sequence of the LUT corresponds to a duty cycle, and wherein the LUT comprises a range of binary sequences representing a range of approximately linearly distributed duty cycles.

22. The system of claim 21, wherein at least one sequence having binary values that have a maximum number of binary “

0”

s between each binary “

1”

for a duty cycle less than or equal to 50%.

23. The system of claim 21, wherein at least one sequence having binary values that have a maximum number of binary “

1”

s between each binary “

0”

for a duty cycle greater than 50%.

24. The system of claim 21, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate an approximately linearly distributed duty cycle;

wherein the sample space defines the maximum number of samples that are used for each sequence.

25. The system of claim 18, wherein each of the patterns form a unique sequence, and each sequence representing a unique duty cycle and phase response, and wherein each sequence being tested to generate an actual phase response for each sequence and compared to a target phase response, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles corresponding to a first and second phase responses that are closest to the target phase response, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate sequence that approximately generates the target phase response.

26. The system of claim 18, wherein the plurality of binary sequences representing a range of approximately linearly distributed phase responses.

27. The system of claim 18, wherein the data comprises image data and the target phase response represents a bit depth level of the image data.

28. The system of claim 18, wherein the light modulation device comprises spatial light modulation (SLM) circuitry.

29. The system of claim 18, wherein the light modulation device comprises liquid crystal on silicon (LCoS) circuitry.

30. A non-transitory machine-readable storage medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to:

generate a first set of patterns, each pattern of the first set of patterns generated as;

for n=N−

1 . . . 1, n leading “

0”

s plus a trailing “

1”

;

where n is an index ranging from 1 to N, and N represents a number of target phase responses; and

generate a second set of patterns, each pattern of the second set of patterns generated as;

for n=1 to N−

2, generate pattern {01x}, where x=n number of trailing “

1”

s; and

determine, from among the first set of patterns and the second set of patterns, a pattern that matches a linearly distributed duty cycle and repeating that sample over a sample space being defined as the maximum number of samples that are used for each sequence; and

determine, from among the first set of patterns and the second set of patterns, a first pattern that is a closest match to a linearly distributed duty cycle and a second pattern that is a second closest match to the a linearly distributed duty cycle, and interpolating the first duty cycle and the second duty cycle and repeating the first and second pattern over the sample space.

31. The non-transitory machine-readable storage medium of claim 30, wherein the patterns of binary values also include a pattern of repeating “

0”

s over the sample space and pattern of repeating “

1”

s over a sample space.

32. The non-transitory machine-readable storage medium of claim 30, wherein each binary sequence of the LUT corresponds to a duty cycle, and wherein the LUT comprises a range of binary sequences representing a range of approximately linearly distributed duty cycles.

33. The non-transitory machine-readable storage medium of claim 32, wherein at least one sequence having binary values that have a maximum number of binary “

0”

s between each binary “

1”

for a duty cycle less than or equal to 50%.

34. The non-transitory machine-readable storage medium of claim 32, wherein at least one sequence having binary values that have a maximum number of binary “

1”

s between each binary “

0”

for a duty cycle greater than 50%.

35. The non-transitory machine-readable storage medium of claim 30, wherein each of the patterns form a unique sequence, and each sequence representing a unique duty cycle and phase response, and wherein each sequence being tested to generate an actual phase response for each sequence and compared to a target phase response, wherein at least one binary sequence generated by an interpolation of a first and second duty cycles corresponding to a first and second phase responses that are closest to the target phase response, and the at least one binary sequence being formed by alternating a first pattern associated with the first duty cycle and a second pattern associated with the second duty cycle over a sample space to generate sequence that approximately generates the target phase response.

36. The non-transitory machine-readable storage medium of claim 30, wherein the plurality of binary sequences representing a range of approximately linearly distributed phase responses.

37. A method of generating a look-up table of sequences to drive a pixel of display circuitry, comprising:

generate a plurality of binary sequences, each sequence having a plurality of binary values arranged over a sample space, and each sequence corresponding to a duty cycles;

measure a phase response and/or ripple error of each sequence by applying each sequence to the pixel over the sample space;

determining if a phase response of a given sequence is within a defined tolerance of a target phase response; and

determining if a phase response of a given sequence is outside the defined tolerance and interpolating two duty cycles that are closets to the target phase response to generate a sequence that generates a phase response that is within the defined tolerance of the target phase response.

38. The method of claim 37, wherein at least one sequence comprises a pattern that includes a binary pattern having a maximum number of “

0”

s;

wherein the pattern is repeated over the sample space.

39. The method of claim 37, wherein at least one sequence comprises a pattern that includes a binary pattern having a maximum number of “

1”

s;

wherein the pattern is repeated over the sample space.

40. The method of claim 37, further comprising:

determining if each sequence matches a range of distributed target duty cycles; and

determining first pattern that is a closest match to a distributed target duty cycle and a second pattern that is a second closest match to the distributed target duty cycle, and interpolating the first duty cycle and the second duty cycle and repeating the first and second pattern over the sample space.

41. The method of claim 37, wherein the patterns of binary values also include a pattern of repeating “

0”

s over the sample space and pattern of repeating “

1”

s over a sample space.

42. The method of claim 37, wherein each binary sequence of the LUT corresponds to a duty cycle, and wherein the LUT comprises a range of binary sequences representing a range of approximately linearly distributed duty cycles.

43. The method of claim 37, wherein at least one sequence having binary values that have a maximum number of binary “

0”

s between each binary “

1”

for a duty cycle less than or equal to 50%.

44. The method of claim 37, wherein at least one sequence having binary values that have a maximum number of binary “

1”

s between each binary “

0”

for a duty cycle greater than 50%.

45. A method of generating a look-up table of sequences to drive at least one pixel of display circuitry, comprising:

generating a plurality of binary sequences, each sequence having a plurality of binary values arranged for a period of drive time, and wherein each of the plurality of binary sequences has a corresponding duty cycle and a target phase response;

applying each of the plurality of binary sequences to the at least one pixel over the period of drive time;

measuring a phase response from the at least one pixel after application of each of the plurality of binary sequences to the at least one pixel and generating phase response data;

identifying, for each of the plurality of binary sequences, a first measured phase response that is closest to an amount of the target phase response associated with each of the generated plurality of sequences and a second measured phase response that is second closest to the amount of target phase response associated with each of the generated plurality of sequences, and generating at least two identified phase responses; and

generating an interpolated binary sequence based on the phase response data and the target phase response.

46. The method of claim 45, wherein each of the measured phase responses is associated with the duty cycle associated with the binary sequence that generated the measured phase response, and wherein the step of generating an interpolated binary sequence comprises:

calculating a duty cycle difference between duty cycle amounts associated with each of the at least two identified phase responses;

calculating a phase response difference between phase amounts of the first measured phase response and the second measured phase response; and

generating slope data based on the duty cycle difference and the phase response difference.

47. The method of claim 46, wherein the interpolated binary sequence is derived from an interpolated duty cycle, and wherein the step of interpolating the duty cycle comprises:

identifying the duty cycle associated with the first measured phase response;

calculating a difference between the target phase response and the first measured phase response and generating new target phase response data;

multiplying the slope data with the new target response data and generated a factored phase response data; and

adding the factored phase response data to the identified duty cycle associated with the first measured phase response.