SCANNING SIGNAL LINE DRIVE CIRCUIT, DISPLAY DEVICE PROVIDED WITH SAME, AND DRIVE METHOD FOR SCANNING SIGNAL LINE

• US 20200135132A1
• Filed: 10/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: TANAKA, Kohhei, WATANABE, Takuya, IWASE, Yasuaki
• Granted Patent: US 10,825,414 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Claims

1. A scanning signal line drive circuit for selectively driving a plurality of scanning signal lines provided in a display portion of a display device, the circuit comprising:

a first scanning signal line driver portion configured to be operated in accordance with a multi-phase clock signal and disposed near first ends of the plurality of scanning signal lines; and

a second scanning signal line driver portion configured to be operated in accordance with the multi-phase clock signal and disposed near second ends of the plurality of scanning signal lines, wherein,

the first scanning signal line driver portion includes;

a first shift register having a plurality of first bistable circuits cascaded together and provided in one-to-one correspondence with a plurality of scanning signal line groups, each group consisting of two or more adjacent scanning signal lines selected from the plurality of scanning signal lines; and

a plurality of buffer circuits connected to the first ends of the plurality of scanning signal lines in one-to-one correspondence to the plurality of scanning signal lines,

the second scanning signal line driver portion includes;

a second shift register having a plurality of second bistable circuits cascaded together and provided in one-to-one correspondence with a plurality of scanning signal line groups, each group consisting of two or more adjacent scanning signal lines selected from the plurality of scanning signal lines; and

a plurality of buffer circuits connected to the second ends of the plurality of scanning signal lines in one-to-one correspondence to the plurality of scanning signal lines,

the plurality of scanning signal lines are grouped such that none of the scanning signal line groups corresponding to the first bistable circuits are identical to any of the scanning signal line groups corresponding to the second bistable circuits,

the first and second shift registers are configured such that the first bistable circuits and the second bistable circuits sequentially output active signals out of phase with each other in accordance with the grouping of the plurality of scanning signal lines,

the first and second scanning signal line driver portions are configured such that;

for each of the groups respectively corresponding to the first bistable circuits, the buffer circuits that are respectively connected to the first ends of the two or more scanning signal lines in the group are supplied with clock signals included in the multi-phase clock signal and being out of phase with each other,

for each of the groups respectively corresponding to the second bistable circuits, the buffer circuits that are respectively connected to the second ends of the two or more scanning signal lines in the group are supplied with clock signals included in the multi-phase clock signal and being out of phase with each other, and

the buffer circuits that are respectively connected to the first and second ends of the same scanning signal line are supplied with the same clock signal in the multi-phase clock signal,

the buffer circuits that are respectively connected to the first ends of the plurality of scanning signal lines each include a buffer transistor that has a control terminal at which to receive an output signal from a corresponding first bistable circuit, a first conductive terminal at which to receive the supplied clock signal, and a second conductive terminal connected to the first end of a corresponding scanning signal line, and

the buffer circuits that are respectively connected to the second ends of the plurality of scanning signal lines each include a buffer transistor that has a control terminal at which to receive an output signal from a corresponding second bistable circuit, a first conductive terminal at which to receive the supplied clock signal, and a second conductive terminal connected to the second end of a corresponding scanning signal line.

2. The scanning signal line drive circuit according to claim 1, wherein,

the buffer circuits that are respectively connected to the first ends of the plurality of scanning signal lines and the buffer circuits that are respectively connected to the second ends of the plurality of scanning signal lines each further include a capacitor and a transmission gate,

the control terminal of the buffer transistor is connected to the second conductive terminal via the capacitor and to an output terminal of the corresponding bistable circuit via the transmission gate, and

the transmission gate is configured to transmit a voltage within a range between a predetermined value corresponding to a power supply voltage for turning on the buffer transistor among power supply voltages for the first and second scanning signal line driver portions and a voltage value for turning off the buffer transistor, and to prevent a voltage that turns on the buffer transistor but is out of the range from being transmitted.

3. The scanning signal line drive circuit according to claim 2, wherein,

the transmission gate includes a field-effect transistor having a control terminal to which a power supply voltage for either the first or second scanning signal line driver portion is provided for turning on the buffer transistor in the buffer circuit that includes the transmission gate, and

the control terminal of the buffer transistor in the buffer circuit that includes the transmission gate is connected to the output terminal of the corresponding bistable circuit via the field-effect transistor.

4. The scanning signal line drive circuit according to claim 2, wherein,

the transmission gate includes two field-effect transistors of the same channel type, the two field-effect transistors being connected in parallel,

each of the two field-effect transistors has a control terminal to which one clock signal included in the multi-phase clock signal is provided such that clock signals provided to the control terminals of the two field-effect transistors are opposite in phase, and

the control terminal of the buffer transistor in the buffer circuit that includes the transmission gate is connected to the output terminal of the corresponding bistable circuit via the two field-effect transistors.

5. The scanning signal line drive circuit according to claim 1, wherein,

the first bistable circuits are in one-to-one correspondence with a plurality of scanning signal line groups, each consisting of two adjacent scanning signal lines selected from the plurality of scanning signal lines,

the second bistable circuits are in one-to-one correspondence with a plurality of scanning signal line groups, each consisting of two adjacent scanning signal lines selected from the plurality of scanning signal lines,

for each bistable circuit of the first and second bistable circuits, the buffer circuit that is connected to one of two scanning signal lines in a group corresponding to the bistable circuit and receives an output signal from the bistable circuit is a first-type buffer circuit that includes the buffer transistor as a first transistor and further includes a first capacitor,

the control terminal of the first transistor is connected to the second conductive terminal of the first transistor via the first capacitor and also directly connected to the output terminal of the corresponding bistable circuit,

for each bistable circuit of the first and second bistable circuits, the buffer circuit that is connected to the other of the two scanning signal lines in the group corresponding to the bistable circuit and receives the output signal from the bistable circuit is a second-type buffer circuit that includes the buffer transistor as a second transistor and further includes a second capacitor and a transmission gate,

the control terminal of the second transistor is connected to the second conductive terminal of the second transistor via the second capacitor as well as to the output terminal of the corresponding bistable circuit via the transmission gate, and

the transmission gate is configured to transmit a voltage within a range between a predetermined value corresponding to a power supply voltage for turning on the second buffer transistor among power supply voltages for the first and second scanning signal line driver portions and a voltage value for turning off the second buffer transistor, and to prevent a voltage that turns on the second buffer transistor but is out of the range from being transmitted.

6. The scanning signal line drive circuit according to claim 5, wherein, either or both of different size setting for the first and second transistors and different capacitance value setting for the first and second transistors are performed so as to reduce or eliminate a difference in scanning signal line drive capability between the first-type buffer circuit and the second-type buffer circuit.

7. The scanning signal line drive circuit according to claim 5, wherein,

the transmission gate includes a field-effect transistor having a control terminal to which a power supply voltage for either the first or second scanning signal line driver portion is provided for turning on the buffer transistor in the buffer circuit that includes the transmission gate, and

the control terminal of the buffer transistor in the buffer circuit that includes the transmission gate is connected to the output terminal of the corresponding bistable circuit via the field-effect transistor.

8. The scanning signal line drive circuit according to claim 5, wherein,

the transmission gate includes two field-effect transistors of the same channel type, the two field-effect transistors being connected in parallel,

each of the two field-effect transistors has a control terminal to which one clock signal included in the multi-phase clock signal is provided such that clock signals provided to the control terminals of the two field-effect transistors are opposite in phase, and

the control terminal of the buffer transistor in the buffer circuit that includes the transmission gate is connected to the output terminal of the corresponding bistable circuit via the two field-effect transistors.

9. A display device having a display portion provided with a plurality of data signal lines, a plurality of scanning signal lines crossing the data signal lines, and a plurality of pixel forming portions arranged in a matrix along the data signal lines and the scanning signal lines, the device comprising:

a data signal line drive circuit configured to drive the data signal lines;

a scanning signal line drive circuit of claim 1; and

a display control circuit configured to control the data signal line drive circuit and the scanning signal line drive circuit.

10. The display device according to claim 9, wherein the scanning signal line drive circuit and the display portion are integrally formed on the same substrate.

11. The display device according to claim 9, wherein,

the display control circuit controls the data signal line drive circuit and the scanning signal line drive circuit such that one frame period includes a non-scanning period in which the scanning signal lines are stopped from being driven between scanning periods in which the scanning signal lines are driven,

the multi-phase clock signal consists of a plurality of clock signals out of phases with each other, voltage levels of the clock signals alternating between ON and OFF levels in predetermined cycles during the scanning period, the ON and OFF levels respectively corresponding to selection and deselection of the scanning signal lines, and

the display control circuit generates the multi-phase clock signal such that, before the non-scanning period starts, the voltage levels of the clock signals are sequentially changed from the ON level to the OFF level and kept at the OFF level, and after the non-scanning period, the voltage levels of the clock signals are sequentially changed from the OFF level to the ON level and then alternate between the ON level and the OFF level in the predetermined cycles.

12. A drive method for selectively driving a plurality of scanning signal lines provided in a display portion of a display device, the method comprising:

a first scanning signal line drive step of driving the plurality of scanning signal lines from first ends of the plurality of scanning signal lines in accordance with a multi-phase clock signal; and

a second scanning signal line drive step of driving the plurality of scanning signal lines from second ends of the plurality of scanning signal lines in accordance with the multi-phase clock signal, wherein,

the first scanning signal line drive step includes;

a first shift operation step of sequentially outputting active signals from a plurality of first bistable circuits constituting a first shift register by being cascaded together and provided in one-to-one correspondence with a plurality of scanning signal line groups, each group consisting of two or more adjacent scanning signal lines selected from the plurality of scanning signal lines; and

a first charge/discharge step of charging or discharging the plurality of scanning signal lines by a plurality of buffer circuits connected to the first ends of the plurality of scanning signal lines in one-to-one correspondence with the plurality of scanning signal lines,

the second scanning signal line drive step includes;

a second shift operation step of sequentially outputting active signals from a plurality of second bistable circuits constituting a second shift register by being cascaded together and provided in one-to-one correspondence with a plurality of scanning signal line groups, each group consisting of two or more adjacent scanning signal lines selected from the plurality of scanning signal lines; and

a second charge/discharge step of charging or discharging the plurality of scanning signal lines by a plurality of buffer circuits connected to the second ends of the plurality of scanning signal lines in one-to-one correspondence with the plurality of scanning signal lines,

the plurality of scanning signal lines are grouped such that none of the scanning signal line groups corresponding to the first bistable circuits are identical to any of the scanning signal line groups corresponding to the second bistable circuits,

in the first and second shift operation steps, the first bistable circuits and the second bistable circuits sequentially output active signals out of phase with each other in accordance with the grouping of the plurality of scanning signal lines,

the first charge/discharge step includes a first clock supply step of supplying clock signals included in the multi-phase clock signal and being out of phase with each other, to the buffer circuits respectively connected to the first ends of the two or more scanning signal lines in each of the groups respectively corresponding to the first bistable circuits,

the second charge/discharge step includes a second clock supply step of supplying clock signals included in the multi-phase clock signal and being out of phase with each other, to the buffer circuits respectively connected to the second ends of the two or more scanning signal lines in each of the groups respectively corresponding to the second bistable circuits,

in the first and second clock supply steps, the buffer circuits that are respectively connected to the first and second ends of the same scanning signal line are supplied with the same clock signal in the multi-phase clock signal,

in the first charge/discharge step, by means of buffer transistors each having a control terminal at which to receive an output signal from a corresponding first bistable circuit, a first conductive terminal at which to receive the supplied clock signal, and a second conductive terminal connected to the first end of a corresponding scanning signal line, the buffer circuits that are respectively connected to the first ends of the plurality of scanning signal lines charge or discharge the corresponding scanning signal lines from the first ends in accordance with the supplied clock signals when active signals are being outputted by the corresponding first bistable circuits, and

in the second charge/discharge step, by means of buffer transistors each having a control terminal at which to receive an output signal from a corresponding second bistable circuit, a first conductive terminal at which to receive the supplied clock signal, and a second conductive terminal connected to the second end of a corresponding scanning signal line, the buffer circuits that are respectively connected to the second ends of the plurality of scanning signal lines charge or discharge the corresponding scanning signal lines from the second ends in accordance with the supplied clock signals when active signals are being outputted by the corresponding second bistable circuits.

13. The drive method according to claim 12, wherein,

the buffer circuits that are respectively connected to the first ends of the plurality of scanning signal lines and the buffer circuits that are respectively connected to the second ends of the plurality of scanning signal lines each further include a capacitor and a transmission gate,

the control terminal of the buffer transistor is connected to the second conductive terminal via the capacitor and to an output terminal of the corresponding bistable circuit via the transmission gate, and

the transmission gate is configured to transmit a voltage within a range between a predetermined value corresponding to a power supply voltage for turning on the buffer transistor among power supply voltages for the first and second scanning signal line driver portions and a voltage value for turning off the buffer transistor, and to prevent a voltage that turns on the buffer transistor but is out of the range from being transmitted.

14. The drive method according to claim 12, wherein,

the first bistable circuits are in one-to-one correspondence with a plurality of scanning signal line groups, each consisting of two adjacent scanning signal lines selected from the plurality of scanning signal lines,

the second bistable circuits are in one-to-one correspondence with a plurality of scanning signal line groups, each consisting of two adjacent scanning signal lines selected from the plurality of scanning signal lines,

for each bistable circuit of the first and second bistable circuits, the buffer circuit that is connected to one of two scanning signal lines in a group corresponding to the bistable circuit and receives an output signal from the bistable circuit is a first-type buffer circuit that includes the buffer transistor as a first transistor and further includes a first capacitor,

the control terminal of the first transistor is connected to the second conductive terminal of the first transistor via the first capacitor as well as directly connected to the output terminal of the corresponding bistable circuit,

for each bistable circuit of the first and second bistable circuits, the buffer circuit that is connected to the other of the two scanning signal lines in the group corresponding to the bistable circuit and receives the output signal from the bistable circuit is a second-type buffer circuit that includes the buffer transistor as a second transistor and further includes a second capacitor and a transmission gate,

the control terminal of the second transistor is connected to the second conductive terminal of the second transistor via the second capacitor as well as to the output terminal of the corresponding bistable circuit via the transmission gate, and

the transmission gate is configured to transmit a voltage within a range between a predetermined value corresponding to a power supply voltage for turning on the second buffer transistor among power supply voltages for the first and second scanning signal line drive steps and a voltage value for turning off the second buffer transistor, and to prevent a voltage that turns on the second buffer transistor but is out of the range from being transmitted.