Display Method and Display system for Reducing a Double Image Effect

• US 20200135149A1
• Filed: 10/17/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: BenQ Intelligent Technology(Shanghai) Co., Ltd., BenQ Corporation (Qisda Corporation)
• Original Assignee: BenQ Intelligent Technology(Shanghai) Co., Ltd., BenQ Corporation (Qisda Corporation)
• Inventors: Lin, Hsin-Nan
• Granted Patent: US 10,930,248 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0237 Switching ON and OFF the backlight within one frame
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/10 Intensity circuits
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A display method includes changing a first transmission rate of a panel data clock signal to a second transmission rate, changing a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period including a vertical pixel active synchronization interval and a blank interval according to at least the second transmission rate of the panel data clock signal, and merely enabling a backlight device during a time interval of any length within the blank interval. The second transmission rate is greater than the first transmission rate. The second vertical synchronization period is greater than the first vertical synchronization period.

Claims

1. A display method for reducing a double image effect comprising:

changing a first transmission rate of a panel data clock signal to a second transmission rate;

changing a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period comprising a vertical pixel active synchronization interval and a blank interval according to at least the second transmission rate of the panel data clock signal; and

merely enabling a backlight device during a time interval of any length within the blank interval;

wherein the second transmission rate is greater than the first transmission rate, and the second vertical synchronization period is greater than the first vertical synchronization period.

2. The method of claim 1, further comprising:

changing a first horizontal synchronization period of a horizontal synchronization signal to a second horizontal synchronization period;

wherein the second horizontal synchronization period is smaller than the first horizontal synchronization period.

3. The method of claim 1, wherein the vertical pixel active synchronization interval is a constant, when the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, a time length of the blank interval is changed from a first time length to a second time length, and the second time length is greater than the first time length.

4. The method of claim 1, wherein the second vertical synchronization period approaches a maximum vertical synchronization period supported by a display panel.

5. The method of claim 1, wherein changing the first vertical synchronization period of the vertical synchronization signal to the second vertical synchronization period, is to directly select the second vertical synchronization period greater than the first vertical synchronization period from a plurality of vertical synchronization periods supported by a display panel.

6. The method of claim 1, further comprising:

disabling the backlight device outside the blank interval;

wherein the vertical pixel active synchronization interval and an interval for enabling the backlight device are non-overlapped.

7. The method of claim 1, wherein a transmission rate of the panel data clock signal, a horizontal synchronization period of a horizontal synchronization signal, and a vertical synchronization period of the vertical synchronization signal satisfy an equation:

P_DATA=H_TOTAL×

V_TOTAL×

FR

P_DATA is the transmission rate, H_TOTAL is the horizontal synchronization period, V_TOTAL is the vertical synchronization period, and FR is a frame rate constant.

8. The method of claim 1, further comprising:

receiving an image data signal generated by a signal source; and

generating the panel data clock signal according to the image data signal;

wherein a transmission rate of the image data signal is different from the second transmission rate of the panel data clock signal.

9. The method of claim 1, wherein the backlight device is driven by using a backlight pulse width modulation signal, and after the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, a duty cycle of the backlight pulse width modulation signal is smaller than a duty cycle of the vertical synchronization signal.

10. A display method for reducing a double image effect comprising:

acquiring a vertical synchronization period of a vertical synchronization signal of a display panel, the vertical synchronization period including a vertical pixel active synchronization interval and a blank interval; and

merely enabling a backlight device during a time interval of any length within the blank interval;

wherein the vertical pixel active synchronization interval and an interval for enabling the backlight device are non-overlapped, and an occupation ratio of the blank interval to the vertical synchronization period is greater than 5%.

11. The method of claim 10, further comprising:

changing a first transmission rate of a panel data clock signal to a second transmission rate for maximizing the vertical synchronization period;

wherein the second transmission rate is greater than the first transmission rate.

12. A display system comprising:

a display panel comprising a plurality of pixels configured to display an image;

a gate driving circuit coupled to the plurality of pixels;

a data driving circuit coupled to the plurality of pixels;

a timing controller coupled to the gate driving circuit and the data driving circuit and configured to control the gate driving circuit and the data driving circuit;

a backlight device; and

a processor coupled to the timing controller and the backlight device and configured to control the timing controller and the backlight device;

wherein after the processor receives an image data signal, a panel data clock signal is generated, the processor changes a first transmission rate of the panel data clock signal to a second transmission rate, changes a first vertical synchronization period of a vertical synchronization signal to a second vertical synchronization period according to at least the second transmission rate of the panel data clock signal, the second vertical synchronization period comprises a vertical pixel active synchronization interval and a blank interval, and the timing controller controls the gate driving circuit and the data driving circuit for generating the image by driving the plurality of pixels during the vertical pixel active synchronization interval; and

wherein the processor merely enables the backlight device during a time interval of any length within the blank interval, the second transmission rate is greater than the first transmission rate, and the second vertical synchronization period is greater than the first vertical synchronization period.

13. The system of claim 12, wherein the processor changes a first horizontal synchronization period of a horizontal synchronization signal to a second horizontal synchronization period, and the second horizontal synchronization period is smaller than the first horizontal synchronization period.

14. The system of claim 12, wherein the vertical pixel active synchronization interval is a constant, when the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, a time length of the blank interval is changed from a first time length to a second time length, and the second time length is greater than the first time length.

15. The system of claim 12, wherein the second vertical synchronization period approaches a maximum vertical synchronization period supported by the display panel.

16. The system of claim 12, wherein the processor disables the backlight device outside the blank interval, and the vertical pixel active synchronization interval and an interval for enabling the backlight device are non-overlapped.

17. The system of claim 12, wherein a transmission rate of the panel data clock signal, a horizontal synchronization period of a horizontal synchronization signal, and a vertical synchronization period of the vertical synchronization signal satisfy an equation:

P_DATA=H_TOTAL×

V_TOTAL×

FR

P_DATA is the transmission rate, H_TOTAL is the horizontal synchronization period, V_TOTAL is the vertical synchronization period, and FR is a frame rate constant.

18. The system of claim 12, wherein a transmission rate of the image data signal received by the processor is different from the second transmission rate of the panel data clock signal.

19. The system of claim 12, wherein the backlight device is driven by using a backlight pulse width modulation signal, and after the first vertical synchronization period of the vertical synchronization signal is changed to the second vertical synchronization period, a duty cycle of the backlight pulse width modulation signal is smaller than a duty cycle of the vertical synchronization signal.

20. The system of claim 12, wherein the processor directly selects the second vertical synchronization period greater than the first vertical synchronization period from a plurality of vertical synchronization periods supported by the display panel.