MAINTAINING VISIBILITY OF VIRTUAL FUNCTION IN BUS-ALIVE, CORE-OFF STATE OF GRAPHICS PROCESSING UNIT
First Claim
1. A method comprising:
- interrupting power to a processor core in a processing unit concurrently with maintaining power to a bus interface that supports communication between an external bus and a virtual function supported by a physical function implemented in the processor core; and
responding, from the bus interface and concurrently with power being interrupted to the processor core, to a request for the virtual function received over the external bus based on state information associated with the virtual function.
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Accused Products
Abstract
A processing unit includes a processor core that implements a physical function that supports multiple virtual functions. The processing unit includes a bus interface that supports communication between an external bus and the physical and virtual functions implemented using the processor core. During a reset of the processing unit, power is interrupted to the processor core power to the bus interface is maintained. The bus interface responds to requests for the physical and virtual functions received over the external bus concurrently with the power interruption. The bus interface responds based on state information associated with the virtual function. Power is restored to the processor core in response to the reinitialization of the GPU. The bus interface stops responding to requests for the physical and virtual functions received over the bus interface in response to restoring the power to the processor core and forwards requests received over the external bus from the bus interface to the processor core.
9 Citations
20 Claims
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1. A method comprising:
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interrupting power to a processor core in a processing unit concurrently with maintaining power to a bus interface that supports communication between an external bus and a virtual function supported by a physical function implemented in the processor core; and responding, from the bus interface and concurrently with power being interrupted to the processor core, to a request for the virtual function received over the external bus based on state information associated with the virtual function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a processor core configured to implement a physical function that supports virtual functions; and a bus interface configured to support communication between an external bus and the physical and virtual functions implemented using the processor core, wherein power is interrupted to the processor core concurrently with maintaining power supplied to the bus interface, and wherein the bus interface responds to a request for the physical and virtual functions received over the external bus concurrently with power being interrupted to the processor core, and wherein the bus interface is configured to respond based on state information associated with the physical and virtual functions. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method comprising:
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storing, at a bus interface that supports communication between an external bus and a virtual function supported by a physical function implemented using a processor core in a processing unit, state information representing a physical and virtual functions implemented by the processor core; resetting the processing unit by interrupting power to the processor core concurrently with maintaining power to the bus interface; and responding, from the bus interface while power is interrupted to the processor core, to a request for the physical and virtual functions received over the external bus based on the state information associated with the physical and virtual functions. - View Dependent Claims (20)
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Specification