SEMICONDUCTOR MEMORY DEVICE

• US 20200135242A1
• Filed: 07/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: ARAI, Fumitaka, HOSOTANI, Keiji, MOMO, Nobuyuki
• Granted Patent: US 11,074,944 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.

Claims

1. A semiconductor memory device comprising:

a first interconnect;

a second interconnect provided above the first interconnect in a first direction;

a third interconnect provided between the first interconnect and the second interconnect in the first direction;

a fourth interconnect provided between the second interconnect and the third interconnect in the first direction;

a fifth interconnect provided between the second interconnect and the fourth interconnect in the first direction;

a semiconductor layer extending in the first direction, and having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect in the first direction;

a memory cell storing information between the semiconductor layer and the fourth interconnect;

a conductive layer extending in the first direction, and having one end connected to the second interconnect and other end connected to the semiconductor layer in the first direction;

a first insulating layer extending in the first direction, and provided to extend between the third interconnect and the semiconductor layer, between the fourth interconnect and the semiconductor layer, and between the fifth interconnect and the conductive layer;

an oxide semiconductor layer extending in the first direction, and provided to extend between the fourth interconnect and the first insulating layer and between the fifth interconnect and the first insulating layer; and

a second insulating layer extending in the first direction, and provided to extend between the fourth interconnect and the oxide semiconductor layer and between the fifth interconnect and the oxide semiconductor layer.

2. The device according to claim 1, wherein

the first and second interconnects extend in a second direction intersecting the first direction, and the third, fourth, and fifth interconnects extend in a third direction intersecting the first and second directions.

3. The device according to claim 1, wherein

the conductive layer includes:

a first portion connected to a top surface of the semiconductor layer, and extending in the first direction; and

a second portion connected to a top surface of the first portion and to the oxide semiconductor layer.

4. The device according to claim 3, wherein

the conductive layer further includes a third portion which is connected to a top surface of the second portion and extends in the first direction to be connected to the second interconnect.

5. The device according to claim 1, wherein

the first insulating layer is in contact with a lower surface of a portion of the conductive layer that is connected to the oxide semiconductor layer.

6. The device according to claim 1, wherein

one end of the oxide semiconductor layer is located between the third interconnect and the fourth interconnect in the first direction.

7. The device according to claim 1, further comprising:

a first transistor includes the third interconnect and the semiconductor layer; and

a second transistor includes the fifth interconnect and the oxide semiconductor layer.

8. The device according to claim 1, wherein

the first interconnect is a bit line, and the second interconnect is a source line.

9. A semiconductor memory device comprising:

a first interconnect;

a second interconnect arranged adjacently to the first interconnect in a first direction;

a third interconnect arranged adjacently to the second interconnect in the first direction;

a fourth interconnect provided above the first interconnect in a second direction intersecting the first direction;

a fifth interconnect arranged adjacently to the fourth interconnect in the first direction;

a sixth interconnect arranged adjacently to the fifth interconnect in the first direction;

a seventh interconnect provided between the first interconnect and the fourth interconnect, between the second interconnect and the fifth interconnect, and between the third interconnect and the sixth interconnect;

an eighth interconnect provided between the seventh interconnect and the fourth interconnect, between the seventh interconnect and the fifth interconnect, and between the seventh interconnect and the sixth interconnect;

a ninth interconnect provided between the eighth interconnect and the fourth interconnect, between the eighth interconnect and the fifth interconnect, and between the eighth interconnect and the sixth interconnect;

a first pillar extending in the second direction, having one end electrically coupled to the first interconnect and other end electrically coupled to the fourth interconnect, and is provided through the seventh interconnect, the eighth interconnect, and the ninth interconnect;

a second pillar adjacent to the first pillar in the first direction, extending in the second direction, and having one end electrically coupled to the third interconnect and other end electrically coupled to the sixth interconnect;

a third pillar having one end electrically coupled to the second interconnect and other end electrically coupled to the fifth interconnect, provided between the first pillar and the second pillar in the first direction, and provided at a different position from the first pillar and the second pillar in a third direction intersecting the first and second directions,

wherein the first pillar includes;

a first semiconductor layer extending in the second direction, and having one end located between the eighth interconnect and the ninth interconnect and other end connected to the first interconnect in the second direction;

a first memory cell storing information between the first semiconductor layer and the eighth interconnect;

a first conductive layer extending in the second direction, and having one end connected to the fourth interconnect and other end connected to the first semiconductor layer in the second direction;

a first insulating layer extending in the second direction, and provided to extend between the seventh interconnect and the first semiconductor layer, between the eighth interconnect and the first semiconductor layer, and between the ninth interconnect and the first conductive layer;

a first oxide semiconductor layer extending in the second direction, and provided to extend between the eighth interconnect and the first insulating layer and between the ninth interconnect and the first insulating layer; and

a second insulating layer extending in the second direction, and provided to extend between the eighth interconnect and the first oxide semiconductor layer and between the ninth interconnect and the first oxide semiconductor layer.

10. The device according to claim 9, wherein

the second pillar includes:

a second semiconductor layer extending in the second direction, and having one end located between the eighth interconnect and the ninth interconnect and other end connected to the third interconnect in the second direction;

a second memory cell storing information between the second semiconductor layer and the eighth interconnect;

a second conductive layer extending in the second direction, and having one end connected to the sixth interconnect and other end connected to the second semiconductor layer in the second direction;

a third insulating layer extending in the second direction, and provided to extend between the seventh interconnect and the second semiconductor layer, between the eighth interconnect and the second semiconductor layer, and between the ninth interconnect and the second conductive layer;

a second oxide semiconductor layer extending in the second direction, and provided to extend between the eighth interconnect and the third insulating layer and between the ninth interconnect and the third insulating layer; and

a fourth insulating layer extending in the second direction, and provided to extend between the eighth interconnect and the second oxide semiconductor layer and between the ninth interconnect and the second oxide semiconductor layer, and

the third pillar includes;

a third semiconductor layer extending in the second direction, and having one end located between the eighth interconnect and the ninth interconnect and other end connected to the second interconnect in the second direction;

a third memory cell storing information between the third semiconductor layer and the eighth interconnect;

a third conductive layer extending in the second direction, and having one end connected to the fifth interconnect and other end connected to the third semiconductor layer in the second direction;

a fifth insulating layer extending in the second direction, and provided to extend between the seventh interconnect and the third semiconductor layer, between the eighth interconnect and the third semiconductor layer, and between the ninth interconnect and the third conductive layer;

a third oxide semiconductor layer extending in the second direction, and provided to extend between the eighth interconnect and the fifth insulating layer and between the ninth interconnect and the fifth insulating layer; and

a sixth insulating layer extending in the second direction, and provided to extend between the eighth interconnect and the third oxide semiconductor layer and between the ninth interconnect and the third oxide semiconductor layer.

11. The device according to claim 9, wherein

the first to sixth interconnects extend in the third direction, and the seventh to ninth interconnects extend in the first direction.

12. The device according to claim 9, wherein

the first conductive layer includes:

a first portion connected to a top surface of the first semiconductor layer and extending in the second direction; and

a second portion connected to a top surface of the first portion and to the first oxide semiconductor layer.

13. The device according to claim 12, wherein

the first conductive layer further includes a third portion which is connected to a top surface of the second portion and extends in the second direction to be connected to the fourth interconnect.

14. The device according to claim 9, further comprising:

a first transistor includes the seventh interconnect and the first semiconductor layer; and

a second transistor includes the ninth interconnect and the first oxide semiconductor layer.

15. The device according to claim 9, wherein

the first interconnect is a bit line, and the second interconnect is a source line.

16. A semiconductor memory device comprising:

a bit line;

a source line;

a pillar extending in a first direction that is directed from the bit line to the source line, and including a semiconductor layer;

first, second, and third conductive layers arranged along the first direction, and facing a side surface of the pillar;

a first transistor arranged at a first intersection of the first conductive layer and the pillar;

a memory cell arranged at a second intersection of the first conductive layer and the pillar, and including a charge storing layer constituted by an oxide semiconductor layer arranged between the semiconductor layer and the second conductive layer; and

a second transistor arranged at a third intersection of the third conductive layer and the pillar,

wherein a first end of the oxide semiconductor layer in the first direction is electrically coupling to the source line via the second transistor, and

a second end of the oxide semiconductor layer in the first direction is located between the first intersection and the second intersection.

17. The device according to claim 16, wherein

a third end of the semiconductor layer in the first direction is located between the second intersection and the third intersection, and

a fourth end of the semiconductor layer in the first direction is in contact with the bit line.

18. The device according to claim 16, wherein

a channel region of the first transistor and a channel region of the memory cell are arranged in the semiconductor layer.

19. The device according to claim 16, wherein

a channel region of the second transistor is arranged in the oxide semiconductor layer.