MEMORY DEVICE WITH SELECTIVE PRECHARGING

• US 20200135245A1
• Filed: 07/26/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: McCombs, Ed
• Granted Patent: US 10,861,513 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.

Claims

1. An electronic device, comprising:

a memory device, comprising;

a first memory cell operably connected to one or more first column signal lines;

a second memory cell operably connected to one or more second column signal lines; and

precharge circuitry operably connected to the one or more first and the one or more second column signal lines, wherein the precharge circuitry is operable to;

precharge the one or more first column signal lines to a first voltage level when the first memory cell is to be accessed; and

precharge the one or more second column signal lines to a second voltage level when the first memory cell is to be accessed, wherein the second voltage level is less than the first voltage level.

2. The electronic device of claim 1, wherein the one or more first column signal lines and the one or more second column signal lines each comprise a bit line and a bit line bar.

3. The electronic device of claim 1, wherein the precharge circuitry comprises:

precharge circuits;

first switch circuitry operably connected to the precharge circuits; and

second switch circuitry operably connected to the precharge circuits.

4. The electronic device of claim 3, wherein:

the precharge circuits comprise;

a first precharge circuit operably connected to the one or more first column signal lines; and

a second precharge circuit operably connected to the one or more second column signal lines;

the first switch circuitry comprises;

a first switch circuit operably connected between the first precharge circuit and a first signal line providing the first voltage level; and

a second switch circuit operably connected between the second precharge circuit and the first signal line providing the first voltage level; and

the second switch circuitry comprises;

a third switch circuit operably connected between the first precharge circuit and a second signal line providing the second voltage level; and

a fourth switch circuit operably connected between the second precharge circuit and the second signal line providing the second voltage level.

5. The electronic device of claim 4, wherein the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit each comprise a p-type transistor.

6. The electronic device of claim 4, wherein:

the first switch circuit and the second switch circuit each comprise a p-type transistor; and

the third switch circuit and the fourth switch circuit each comprise an n-type transistor.

7. The electronic device of claim 4, further comprising a voltage level detector operably connected between the first signal line and the second signal line.

8. The electronic device of claim 4, further comprising:

a voltage level detector operably connected to the second signal line; and

a switch circuit operably connected to the second signal line.

9. The electronic device of claim 1, further comprising timing circuitry operably connected to the processing device.

10. A method of precharging column signal lines operably connected to memory cells in a memory array, the method comprising:

based on a received column address associated with a memory cell to be accessed, determining one or more selected column signal lines operably connected to the memory cell;

precharging the one or more selected column signal lines to a first voltage level; and

precharging one or more unselected column signal lines to a second voltage level that is less than the first voltage level.

11. The method of claim 10, further comprising:

prior to precharging the one or more unselected column signal lines, determining if a voltage level of the second voltage level is below a threshold voltage;

when the voltage level is below the threshold voltage, increasing the voltage level to a voltage level that is greater than the threshold voltage.

12. The method of claim 10, wherein precharging the one or more unselected column signal lines to the second voltage comprises:

precharging the one or more unselected column signal lines for a first amount of time to precharge the one or more unselected column signal lines to the second voltage, where the first amount of time is less than a second amount of time to precharge the one or more selected column signal lines.

13. The method of claim 10, wherein the second voltage level is provided using the first voltage level.

14. The method of claim 10, wherein:

precharging the one or more selected column signal lines to the first voltage level comprises operably connecting the one or more selected column signal lines to a first signal line having the first voltage level using one or more first switch circuits; and

precharging the one or more unselected column signal lines to the first voltage level comprises operably connecting the one or more unselected column signal lines to a second signal line having the second voltage level using one or more second switch circuits.

15. A memory device, comprising:

a first memory cell operably connected to one or more first column signal lines;

a second memory cell operably connected to one or more second column signal lines;

a first precharge circuit operably connected to the one or more first column signal lines;

a second precharge circuit operably connected to the one or more second column signal lines;

a first switch circuit operably connected between the first precharge circuit and a first signal line providing a first voltage level;

a second switch circuit operably connected between the second precharge circuit and the first signal line providing the first voltage level;

a third switch circuit operably connected between the first precharge circuit and a second signal line providing a second voltage level; and

a fourth switch circuit operably connected between the second precharge circuit and the second signal line providing the second voltage level.

16. The memory device of claim 15, wherein the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit each comprise a p-type transistor.

17. The memory device of claim 15, wherein:

the first switch circuit and the second switch circuit each comprise a p-type transistor; and

the third switch circuit and the fourth switch circuit each comprise an n-type transistor.

18. The memory device of claim 15, further comprising a voltage level detector operably connected between the first signal line and the second signal line.

19. The memory device of claim 15, further comprising:

a voltage level detector operably connected to the second signal line; and

a switch circuit operably connected to the second signal line.

20. The memory device of claim 15, wherein the memory device comprises a static random access memory device.