METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME
First Claim
1. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks, the method comprising:
- receiving a CAS command and a write command, wherein the CAS command and the write command conform to an LPDDR5 standard, the write command is dedicated to a first memory rank among the plurality of memory ranks and the write command is not dedicated to a second memory rank among the plurality of memory ranks;
enabling a reception buffer in the first memory rank;
disabling a transmission driver in the first memory rank;
disabling a reception buffer and a transmission driver in the second memory rank;
receiving a data strobe signal pair;
enabling on-die terminal (ODT) circuits of the first memory rank and the second memory rank in response to the write command;
receiving write data signals while the data strobe signal pair is toggled during the enabling of the ODT circuits of the first memory rank and the second memory rank;
receiving the CAS command and a read command, wherein the read command conforms to the LPDDR5 standard, the read command is dedicated to the first memory rank and the read command is not dedicated to the second memory rank;
enabling the transmission driver in the first memory rank;
disabling the reception buffer in the first memory rank;
disabling the reception buffer and the transmission driver in the second memory rank;
disabling the ODT circuit of the first memory rank and enabling the ODT circuit of the second memory rank in response to the read command; and
sending read data signals while the data strobe signal pair is toggled during the disabling of the ODT circuit of the first memory rank and the enabling of the ODT circuit of the second memory rank.
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Abstract
A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
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Citations
20 Claims
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1. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks, the method comprising:
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receiving a CAS command and a write command, wherein the CAS command and the write command conform to an LPDDR5 standard, the write command is dedicated to a first memory rank among the plurality of memory ranks and the write command is not dedicated to a second memory rank among the plurality of memory ranks; enabling a reception buffer in the first memory rank; disabling a transmission driver in the first memory rank; disabling a reception buffer and a transmission driver in the second memory rank; receiving a data strobe signal pair; enabling on-die terminal (ODT) circuits of the first memory rank and the second memory rank in response to the write command; receiving write data signals while the data strobe signal pair is toggled during the enabling of the ODT circuits of the first memory rank and the second memory rank; receiving the CAS command and a read command, wherein the read command conforms to the LPDDR5 standard, the read command is dedicated to the first memory rank and the read command is not dedicated to the second memory rank; enabling the transmission driver in the first memory rank; disabling the reception buffer in the first memory rank; disabling the reception buffer and the transmission driver in the second memory rank; disabling the ODT circuit of the first memory rank and enabling the ODT circuit of the second memory rank in response to the read command; and sending read data signals while the data strobe signal pair is toggled during the disabling of the ODT circuit of the first memory rank and the enabling of the ODT circuit of the second memory rank. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) comprising:
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a first memory rank comprising a first on-die terminal (ODT) circuit, a first reception buffer and a first transmission driver; and a second memory rank comprising a second ODT circuit, a second reception buffer and a second transmission driver, wherein, when a read command dedicated to the first memory rank is received, the first memory rank enables the first transmission driver and disables the first reception buffer and the first ODT circuit, and the second memory rank enables the second ODT circuit and disables the second transmission driver and the second reception buffer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks, the method comprising:
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receiving a CAS command and a read command, wherein the CAS command and the read command conform to an LPDDR5 standard, the read command is dedicated to the first memory rank and the read command is not dedicated to the second memory rank; enabling a transmission driver in the first memory rank; disabling a reception buffer in the first memory rank; disabling a reception buffer and a transmission driver in a second memory rank; disabling an on-die terminal (ODT) circuit of the first memory rank and enabling an ODT circuit of the second memory rank in response to the read command; receiving a data strobe signal, wherein the data strobe signal starts toggling after receiving the read command; and sending read data signals while the data strobe signal is toggled during the disabling of the ODT circuit of the first memory rank and the enabling of the ODT circuit of the second memory rank.
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Specification