APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY

• US 20200135249A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 06/20/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kawamura, Christopher
• Granted Patent: US 10,902,899 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

Claims

1. An apparatus comprising:

a memory comprising;

a memory cell coupled to a first digit line in response to a wordline being set to an active state;

a sense amplifier coupled to the first digit line and to a second digit line, wherein the sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier;

a decoder circuit coupled to the wordline and to the sense amplifier, wherein, in response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

2. The apparatus of claim 1, wherein the decoder circuit is configured to stop the threshold voltage compensation operation after the wordline is set to the active state.

3. The apparatus of claim 2, wherein the decoder circuit is configured to stop the threshold voltage compensation operation less than 3 nanoseconds after the wordline is set to the active state.

4. The apparatus of claim 2, wherein the decoder circuit is configured to stop the threshold voltage compensation operation between 0.25 and 1.25 nanoseconds and after the wordline is set to the active state.

5. The apparatus of claim 1, wherein, during the threshold voltage compensation operation, a first gut node of the sense amplifier is coupled to the second digit line and a second gut node of the sense amplifier is coupled to the first digit line.

6. The apparatus of claim 5, wherein the at least two circuit components include a first transistor coupled between the first gut node and a row Nsense latch (RNL) signal and a second transistor coupled between the second gut node and the RNL signal.

7. The apparatus of claim 1, wherein, during the threshold voltage compensation operation, the first gut node is coupled to the second digit line via a first transistor and a second gut node is coupled to the first digit line via a second transistor.

8. The apparatus of claim 7, wherein, during the threshold voltage compensation operation, the decoder circuit is configured to set a bit line compensation control signal to enable the first and second transistors.

9. An apparatus including:

a sense amplifier configured to, prior to performing a sense operation associated with a memory cell, perform a threshold voltage compensation operation to bias a first digit line and a second digit line such that a voltage difference between the first digit line and the second digit line is equal to a threshold voltage difference between at least two circuit components of the sense amplifier; and

a wordline coupled to the memory cell, wherein the wordline is set to an active state during the threshold voltage compensation operation.

10. The apparatus of claim 9, further comprising a decoder circuit configured to set the wordline to the active state during the threshold voltage compensation operation based on an activation command.

11. The apparatus of claim 10, wherein the decoder circuit includes a row decoder.

12. The apparatus of claim 9, wherein, after the threshold voltage compensation operation, latching the first digit line and the second digit line to respective voltages based on sensed data stored at the memory cell.

13. A method, comprising:

receiving an activate command at a memory;

in response to the activate command, performing a threshold voltage compensation operation to bias digit lines coupled to a sense amplifier of the memory based on a threshold voltage difference between at least two circuit components of the sense amplifier;

during the threshold voltage compensation operation, activating a wordline based on the activate command; and

after the threshold voltage operation, sensing data of a memory cell at the sense amplifier, wherein the memory cell is coupled to a digit line of the digit lines in response to activation of the wordline.

14. The method of claim 13, wherein performing the threshold voltage compensation operation to bias the digit lines coupled to the sense amplifier is based on threshold voltage differences between a first n-type transistor and a second n-type transistor of the sense amplifier.

15. The method of claim 14, wherein the at least two circuit components include a first n-type transistor is coupled between a first gut node of the sense amplifier and a row Nsense latch (RNL) signal and the second n-type transistor is coupled between a second gut node of the sense amplifier and the RNL signal.

16. The method of claim 13, further comprising sensing data of a memory cell coupled to the word line at a predetermined time after activation of the wordline.

17. The method of claim 13, further comprising stopping the threshold voltage compensation operation after the wordline is set to the active state.

18. The method of claim 13, further comprising, during the threshold voltage compensation operation:

coupling a first gut node of the sense amplifier to one of the digit lines; and

coupling a second gut node of the sense amplifier to another of the digit lines.

19. The method of claim 18, further comprising, during the threshold voltage compensation operation, the first gut node is coupled to the one of the digit lines via a first transistor and the second gut node is coupled to the another of the digit lines via a second transistor.

20. The method of claim 19, further comprising, during the threshold voltage compensation operation, setting a bit line compensation control signal to enable the first and second transistors.