RANDOM ACCESS MEMORY

• US 20200135251A1
• Filed: 10/01/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: OSBORNE, Randy, ZHANG, Kevin Xiaoqiang
• Granted Patent: US 10,878,872 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

Claims

1. A memory cell comprising:

a memory cell stack;

a first word line;

a second word line;

a bit line coupled to one end of the memory cell stack;

a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line; and

a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line,

wherein current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

2. The memory cell of claim 1, wherein the memory cell stack includes a magnetic tunneling junction (MTJ) structure.

3. The memory cell of claim 2, wherein the bit line is coupled to a free magnetic layer side of the MTJ structure.

4. The memory cell of claim 1, wherein the memory cell stack includes a resistivity change element.

5. The memory cell of claim 1, wherein the memory cell stack includes a phase change element.

6. The memory cell of claim 1, wherein the first and second unidirectional selectors are diodes.

7. The memory cell of claim 6, wherein a cathode of the first unidirectional selector is coupled to the first word line, and an anode of the second unidirectional selector is coupled to the second word line.

8. The memory cell of claim 6, wherein one of the first and second unidirectional selectors is disposed above the memory cell stack and another of the first and second unidirectional selectors is disposed below the memory cell stack.

9. The memory cell of claim 6, wherein both of the first and second unidirectional selectors are disposed above the memory cell stack.

10. The memory cell of claim 6, wherein both of the first and second unidirectional selectors are disposed below the memory cell stack.

11. The memory cell of claim 1, wherein no transistor is connected to the memory cell stack in the memory cell.

12. A semiconductor device comprising:

memory cells;

main word lines including a first main word line;

associate word lines including a first associate word line; and

bit lines, wherein;

each of the memory cells includes;

a memory cell stack, one end of which is coupled to corresponding one of the bit lines;

a first diode having an anode coupled to another end of the memory cell stack and a cathode coupled to the first main word line; and

a second diode having a cathode coupled to the another end of the memory cell stack and an anode coupled to the first associate word line.

13. The semiconductor device of claim 12, wherein the memory cell stack includes a magnetic tunneling junction (MTJ) structure.

14. The semiconductor device of claim 12, further comprising:

a first word line driver coupled to the main word lines;

a second word line driver coupled to the associate word lines; and

a bit line drivers coupled to the bit lines.

15. The semiconductor device of claim 14, wherein, to read a data from a target memory cell,

the first word line driver is configured to apply a first read voltage to the first main word line coupled to the target memory cell, and applies a second read voltage to remaining main word lines other than the first main word line, the second read voltage being higher than the first read voltage;

and

the bit line driver is configured to apply a third read voltage to one of the bit lines coupled to the target memory cell, the third read voltage being higher than the first read voltage.

16. The semiconductor device of claim 14, wherein, to write a first type data to a target memory cell,

the first word line driver is configured to apply a first write voltage to the first main word line;

the first word line driver is configured to apply a second write voltage to remaining word lines other than the first main word line, the second write voltage being higher than the first write voltage; and

the bit line driver is configured to apply a third write voltage to one of the bit lines coupled to the target memory cell, the third write voltage being higher than the first write voltage.

17. A method of operating a random access memory (RAM), wherein the RAM comprises:

memory cells;

main word lines including a first main word line;

associate word lines including a first associate word line; and

bit lines, wherein;

each of the memory cells includes;

a memory cell stack, one end of which is coupled to a corresponding one of the bit lines;

a first diode having an anode coupled to another end of the memory cell stack and a cathode coupled to the first main word line; and

a second diode having a cathode coupled to the another end of the memory cell stack and an anode coupled to the first associate word line,

the method comprising reading data by;

applying a first read voltage to the first main word line;

applying a second read voltage to remaining main word lines other than the first main word line, the second read voltage being higher than the first read voltage; and

applying a third read voltage to one of the bit lines, the third read voltage being higher than the first read voltage, thereby reading the data from one of the memory cells coupled to the one of the bit lines and the first main word line.

18. The method of claim 17, further comprising applying the second read voltage to the associate word lines.

19. The method of claim 17, further comprising writing first type data by:

applying a first write voltage to the first main word line;

applying a second write voltage to remaining word lines other than the first main word line, the second write voltage being higher than the first write voltage; and

applying a third write voltage to one or more of the bit lines, the third write voltage being higher than the first write voltage, thereby writing the first type data to one or more of the memory cells coupled to the one or more of the bit lines and the first main word line,

wherein the third write voltage is higher than the third read voltage.

20. The method of claim 19, further comprising writing second type data by:

applying a fourth write voltage to the first associate word line;

applying a fifth write voltage to remaining associate word lines other than the first associate word line, the fifth write voltage being smaller than the fourth write voltage; and

applying a sixth write voltage to one or more of the bit lines, the sixth write voltage being smaller than the fourth write voltage, thereby writing the second type data to one or more of the memory cells coupled to the one or more of the bit lines and the first associate word line.