READ CIRCUIT FOR MAGNETIC TUNNEL JUNCTION (MTJ) MEMORY
First Claim
1. A memory device, comprising:
- a magnetic tunnel junction (MTJ) current path, the MTJ current path comprising;
a first current mirror transistor;
a first pull-up read-enable transistor connected in series with the first current mirror transistor;
an MTJ memory cell connected in series with the first pull-up read-enable transistor and including an MTJ memory element and a first access transistor;
a first pull-down read-enable transistor connected in series with the MTJ memory cell; and
a first non-linear resistance device connected in series and between the first pull-up read-enable transistor and the first current mirror transistor, wherein the first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage
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Abstract
In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.
10 Citations
20 Claims
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1. A memory device, comprising:
a magnetic tunnel junction (MTJ) current path, the MTJ current path comprising; a first current mirror transistor; a first pull-up read-enable transistor connected in series with the first current mirror transistor; an MTJ memory cell connected in series with the first pull-up read-enable transistor and including an MTJ memory element and a first access transistor; a first pull-down read-enable transistor connected in series with the MTJ memory cell; and a first non-linear resistance device connected in series and between the first pull-up read-enable transistor and the first current mirror transistor, wherein the first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. The memory device of claim 10, wherein the MTJ memory element comprises:
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a ferromagnetic free layer connected to the bit-line; a ferromagnetic reference layer connected to the source-line; and a non-magnetic barrier layer disposed between and separating the ferromagnetic reference layer and the ferromagnetic free layer.
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11. A memory device, comprising:
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a magnetic tunnel junction (MTJ) current path comprising a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, and a first pull-down read-enable transistor, wherein a source-line is coupled between the MTJ memory cell and the first pull-down read-enable transistor; and
wherein a bit-line is coupled between the first pull-up read-enable transistor and the MTJ memory cell;a reference current path in parallel with the MTJ current path, the reference current path comprising a second current mirror transistor, a second pull-up read-enable transistor, a reference memory cell, and a second pull-down read-enable transistor, wherein a reference bit-line is coupled between the second pull-up read-enable transistor and the reference memory cell, and wherein a reference source-line is coupled between the reference memory cell and the second pull-down read-enable transistor; and a first non-linear resistance device coupled in the MTJ current path between the first pull-up read-enable transistor and the first current mirror transistor, wherein the first non-linear resistance device is configured to increase an effective tunnel magnetoresistance (TMR) of the MTJ current path. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for reading from an MTJ memory device, comprising:
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providing a magnetic tunnel junction (MTJ) current path and a reference current path in parallel with the MTJ current path, wherein the MTJ current path comprises an MTJ memory cell connected in series with a non-linear resistance device; providing a reading voltage (VREAD) to generate an MTJ current (IMTJ) through the MTJ current path and to generate a reference current (IREF) through the reference current path; and comparing the reference current IREF and the MTJ current IMTJ with one another to determine a status of the MTJ memory cell between a first data state having a first resistance and a second data state having a second resistance, the first data state differing from the second data state. - View Dependent Claims (18, 19, 20)
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Specification