CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE

• US 20200135261A1
• Filed: 03/06/2017
• Published: 04/30/2020
• Est. Priority Date: 03/06/2017
• Status: Active Grant

• Current Assignee: Zentel Japan Corporation
• Original Assignee: Zentel Japan Corporation
• Inventors: Haraguchi, Masaru, Kubo, Takashi, Tsukikawa, Yasuhiko, Iga, Hironori, Yasuda, Kenichi, Hamamoto, Takeshi
• Granted Patent: US 10,991,418 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Claims

1. A control device for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the semiconductor memory device comprising:

a plurality of banks, connected to one another by an internal data bus, and each bank being separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, each bank comprising a plurality of subarrays, and each subarray comprising a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines;

a read/write control circuit, controlling reading of data from the semiconductor memory device and writing of data to the semiconductor memory device; and

a transfer control circuit, controlling data transfer inside the semiconductor memory device and setting to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

2. The control device according to claim 1, wherein the transfer control circuit further transmits the first signal value to the semiconductor memory device via a signal line of a bank address of the interface when transmitting a mode register set command of the JEDEC standard to the semiconductor memory device.

3. The control device according to claim 1, wherein the transfer command comprises a word line activation command for activating a word line without activating the sense amplifiers.

4. The control device according to claim 3, wherein the transfer control circuit invalidates a ZQ calibration command of the JEDEC standard, and sets a bit value assigned to the ZQ calibration command to be usable as a bit value of the word line activation command.

5. The control device according to claim 2, wherein the transfer command comprises a sense amplifier activation command for activating the sense amplifiers of one of the subarrays without activating a word line.

6. The control device according to claim 5, wherein when transmitting the mode register set command of the JEDEC standard to the semiconductor memory device by transmitting a second signal value to the semiconductor memory device via the signal line of the bank address of the interface, the transfer control circuit sets a bit value assigned to the mode register set command to be usable as a bit value of the sense amplifier activation command.

7. The control device according to claim 1, wherein the transfer command further includes a transfer read command and a transfer write command for writing data read from a memory cell of a transfer source subarray into a memory cell of a transfer destination subarray without passing through outside of the semiconductor memory device.

8. The control device according to claim 7, wherein the transfer control circuit disables burst chops and auto pre-charge of read and write commands of the JEDEC standard, and when the read and write commands of the JEDEC standard are transmitted to the semiconductor memory device, the transfer control circuit sets bit values assigned to the read command of the JEDEC standard and the write command of the JEDEC standard to be usable as bit values of the transfer read command and the transfer write command by transmitting a third signal value to the semiconductor memory device via at least one of the signal lines of a column address of the interface, respectively.

9. The control device according to claim 3, wherein when the transfer control circuit transfers data inside one of the subarrays in one of the banks, the transfer control circuit transmits a activation command of the JEDEC standard to the semiconductor memory device for activating a word line and the sense amplifiers of one of the subarrays comprising the activated word line and a row address of the word line that contains the transfer source memory cell, and the word line activation command and a row address of a word line comprising the transfer destination memory cell to the semiconductor memory device, and further a pre-charge command of the JEDEC standard to the semiconductor memory device.

10. The control device according to claim 7, wherein the transfer command further comprises a word line activation command that activates a word line without activating the sense amplifiers, and a sense amplifier activation command that activates the sense amplifiers of one of the subarrays without activating a word line, and when transferring data between different subarrays in one of the banks, commands and addresses submitted by the transfer control circuit to the semiconductor memory device comprise:

a activation command of the JEDEC standard, for activating a word line and the sense amplifiers of one of the subarrays comprising the activated word line;

a row address of the word line comprising the transfer source memory cell;

the sense amplifier activation command;

a row address of the sense amplifiers of one of the subarrays comprising another word line comprising the transfer destination memory cell;

the transfer read command and a column address;

the transfer write command and another column address;

the word line activation command and a row address of the word line comprising the transfer destination memory cell; and

a pre-charge command of the JEDEC standard.

11. The control device according to claim 7, wherein, when transferring data between different subarrays in different banks, commands and addresses transmitted by the transfer control device transmits to the semiconductor memory device comprise:

an activation command of the JEDEC standard, for activating a word line and the sense amplifiers of one of the subarrays comprising the activated word line;

a row address of a word line comprising the transfer source memory cell, a row address of a word line comprising the activation command of the JEDEC standard and the transfer destination memory cell;

the transfer read command and a column address;

the transfer write command and another column address;

a pre-charge command of the JEDEC standard.

12. The control device according to claim 1, wherein the transfer control circuit receives subarray information indicating a range of row addresses comprised in each of the subarrays in each of the banks from the semiconductor memory device via at least one signal line of the interface.

13. The control device according to claim 12, wherein the transfer control circuit receives the subarray information from a multipurpose register of the semiconductor memory device using a mode register read command of the JEDEC standard.

14. The control device according to claim 12, wherein the subarray information comprises a number of row addresses comprised in a cycle of one or more of the subarrays periodically arranged in each one of the banks, and another number of row addresses from a beginning of the cycle to a beginning of each subarray included in the cycle.

15. The control device according to claim 12, wherein the transfer control circuit comprising:

a transfer source address register, storing a bank address and a row address of a transfer source bank received from a processor connected to the transfer control circuit,

a transfer destination address register, storing a bank address and a row address of a transfer destination bank received from the processor,

a transfer page number register, storing a number of pages of transfer data received from the processor;

a subarray information register, storing the subarray information received from the semiconductor memory device; and

an address comparison circuit, determining whether to transfer data within a same subarray and whether to transfer data within a same bank based on information stored in the transfer source address register, the transfer destination address register, the transfer page number register and the subarray information register.

16. The control device according to claim 1, wherein the transfer control circuit comprises a transfer start trigger register storing a transfer start trigger received from a processor connected to the transfer control circuit, and a selector connecting one of the read/write control circuit and the transfer control circuit to the semiconductor memory device according to presence or absence of the transfer start trigger stored in the transfer start trigger register.

17. The control device according to one of claim 1, wherein the semiconductor memory device further comprises at least one register connected to the internal data bus, and the transfer control circuit transfers data via the register when transferring data between different subarrays in different banks.

18. The control device according to one of claim 1, wherein the semiconductor memory device further comprises at least one register and an arithmetic circuit connected to the internal data bus, and the transfer control circuit performs an operation on data, read from one of the banks by the arithmetic circuit, and writes data after the operation to one of the banks.

19. The control device according to claim 18, wherein when transmitting a mode register set command of the JEDEC standard to the semiconductor memory device, the arithmetic circuit transmits an operation code of operation by the arithmetic circuit to the semiconductor memory device through an address signal line of the interface.

20. A semiconductor memory device, comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the semiconductor memory device comprising:

an internal bus;

a plurality of banks, connected to one another by the internal data bus, and each of the banks being separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, each of the banks comprising a plurality of subarrays, and each of the subarrays comprising a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines;

a data input/output circuit, connected to a control device via the interface and connected to the banks via the internal data bus, transmitting/receiving data between the control device and the banks; and

a command input circuit, connected to the control device via the interface and receiving a command for controlling the banks from the control device;

wherein the command input circuit, by receiving a first signal value not used in the JEDEC standard from the control device via at least one signal line of the interface, enables an additional transfer command which is not defined in the JEDEC standard but is a transfer command to write data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device.

21. The semiconductor memory device according to claim 20, wherein the command input circuit receives the first signal value from the control device via a signal line of a bank address of the interface when receiving a mode register set command of the JEDEC standard from the control device.

22. The semiconductor memory device according to claim 20, wherein the transfer command comprises a word line activation command for activating a word line without activating the sense amplifiers.

23. The semiconductor memory device according to claim 22, wherein the command input circuit invalidates a ZQ calibration command of the JEDEC standard, and sets a bit value assigned to the ZQ calibration command to be usable as a bit value of the word line activation command.

24. The semiconductor memory device according to claim 20, wherein the transfer command comprises a sense amplifier activation command for activating the sense amplifiers of a subarray without activating a word line.

25. The semiconductor memory device according to claim 24, wherein when the command input circuit receives a mode register set command of the JEDEC standard from the control device, and by receiving a second signal value from the control device via a signal line of a bank address of the interface, the command input circuit sets a bit value assigned to the mode register set command to be usable as a bit value of the sense amplifier activation command.

26. The semiconductor memory device according to claim 20, wherein the transfer command further comprises a transfer read command and a transfer write command for writing data, read from a memory cell of a transfer source subarray, into a memory cell of a transfer destination subarray without passing through outside of the semiconductor memory device.

27. The semiconductor memory device according to claim 26, wherein the command input circuit is configured to:

invalidate burst chops and auto pre-charge of read and write commands of the JEDEC standard;

receive the read and write commands of the JEDEC standard from the control device; and

by receiving a third signal value from the control device via at least one of the plurality of signal lines of the column address of the interface, setting bit values assigned to the read and write commands of the JEDEC standard to be usable as bit values of the transfer read command and the transfer write command, respectively.

28. The semiconductor memory device according to claim 22, wherein commands and addresses received by the command input circuit from the control device comprise:

an activation command of the JEDEC standard, for activating a word line and the sense amplifiers of a subarray including the activated word line;

a row address of word line comprising a memory cell of a transfer source;

the word line activation command;

a row address of a word line comprising a memory cell of a transfer destination; and

a pre-charge command of the JEDEC standard;

thereby, data is transferred within one of the subarrays in one of the banks.

29. The semiconductor memory device according to claim 26, wherein the transfer command further comprises a word line activation command that activates a word line without activating the sense amplifiers, and a sense amplifier activation command for activating the sense amplifiers of a subarray without activating a word line, and commands and addresses received by the command input circuit from the control device comprise:

an activation command of the JEDEC standard, for activating a word line and a sense amplifier of a subarray comprising the activated word line;

a row address of a word line comprising the transfer source memory cell;

the sense amplifier activation command and a row address of a sense amplifier of a subarray comprising a word line comprising the transfer destination memory cell;

the transfer read command and a column address;

the transfer write command and another column address;

the word line activation command and a row address of a word line comprising the transfer destination memory cell; and

a pre-charge command of the JEDEC standard;

thereby, data is transferred between different subarrays in one of the banks and within one of the subarrays in one of the banks.

30. The semiconductor memory device according to claim 26, wherein commands and addresses received by the command input circuit from the control device comprise:

an activation command of the JEDEC standard, for activating a word line and a sense amplifier of a subarray comprising the activated word line and a row address of a word line comprising the transfer source memory cell;

the activation command and a row address of a word line comprising the transfer destination memory cell;

the transfer read command and a column address;

the transfer write command and another column address; and

a pre-charge command of the JEDEC standard;

thereby, data is transferred between different subarrays in different banks,

31. The semiconductor memory device according to claims 20, wherein the command input circuit transmits subarray information indicating a range of row addresses comprised in each of the subarrays in each of the banks to the control device via at least one signal line of the interface.

32. The semiconductor memory device according to claim 31, wherein the command input circuit transmits the subarray information stored in a multipurpose register of the semiconductor memory device to the control device in response to a mode register read command of the JEDEC standard.

33. The semiconductor memory device according to claim 31, wherein the subarray information comprises a number of row addresses comprised in a cycle of one or more of the subarrays periodically arranged in each of the banks and a number of row addresses from the beginning of the cycle to the beginning of each subarray comprised in the cycle.

34. The semiconductor memory device according to claim 20, wherein the semiconductor memory device further comprises at least one register connected to the internal data bus, and the command input circuit transfers data via the register when transferring data between different subarrays in different banks.

35. The semiconductor memory device according to claim 20, wherein the semiconductor memory device further comprises at least one register and an arithmetic circuit connected to the internal data bus, and the command input circuit performs an operation on data, read from one of the banks by the arithmetic circuit, and writes the data after the operation to one of the banks.

36. The semiconductor memory device according to claim 35, wherein when the arithmetic circuit receives a mode register set command of the JEDEC standard from the control device, the arithmetic circuit receives an operation code of the operation by the arithmetic circuit from the control device via the signal line of the address of the interface.

37. A control method for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM and a plurality of banks connected to one another by an internal data bus, each bank being separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, each bank comprising a plurality of subarrays, and each subarray comprising a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines, the control method comprising a step of:

enabling an additional transfer command not specified in the JEDEC standard and a transfer command to write data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by receiving from a control device a first signal value not used in the JEDEC standard via at least one signal line of the interface.