PERFORMING AN ON DEMAND REFRESH OPERATION OF A MEMORY SUB-SYSTEM

• US 20200135264A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brady, Michael T.
• Granted Patent: US 10,692,559 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2211/4061 : Calibration or ate or cycle tuning

Abstract

A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.

Claims

1. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to;

identify a temporal attribute of user data stored in the memory component;

determine that the identified temporal attribute satisfies a time condition;

upon determining that the identified temporal attribute satisfies the time condition, provide an indication whether a refresh operation of the user data improves performance of the memory component;

receive a user input indicating to perform the refresh operation of the memory component; and

perform the refresh operation of the memory component.

2. The system of claim 1, wherein the temporal attribute represents an amount of time that has elapsed since the user data was stored in the memory component, wherein to determine that the identified temporal attribute satisfies the first time condition, the processing device is to:

determine that the amount of time that has elapsed exceeds a threshold amount of time.

3. The system of claim 1, wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide at least one of:

the indication identifying that the refresh operation of the user data improves performance of the memory component;

or

the indication identifying that the refresh operation of the user data does not improve performance of the memory component.

4. The system of claim 1, wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide a probability of success of the refresh operation of the user data to improve performance of the memory component.

5. The system of claim 1, wherein to provide the indication whether the refresh operation of the user data improves performance of the memory component, the processing device is to:

provide the indication to a host system coupled to the memory component to identify whether the refresh operation of the user data improves performance of the memory component.

6. The system of claim 1, wherein to perform the refresh operation of the memory component, the processing device is to:

erase the user data from a first location of the memory component; and

perform a write operation on a second location of the memory component using the user data.

7. The system of claim 6, wherein the first location is the same as the second location.

8. The system of claim 1, wherein the processing device is further to:

provide one or more information associated with the refresh operation, the one or more information comprising one or more of;

a number of total refresh operations attempted in association with memory component;

a number of successful refresh operations attempted in association with the memory component;

a number of unsuccessful refresh operations attempted in association with the memory component;

an average time to complete refresh operations attempted in association with the memory component;

a standard deviation of time to complete refresh operations attempted in association with the memory component;

a first status of the refresh operation;

or

a second status of a previous refresh operation attempted in association with the memory component.

9. The system of claim 1, wherein prior to performing the refresh operation of the memory component, the processing device is to:

determine that a time between the refresh operation and a previously performed refresh operation exceeds a threshold time.

10. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to;

identify a temporal attribute of user data stored in the memory component;

determine that the identified temporal attribute satisfies a time condition;

upon determining that the identified temporal attribute satisfies the time condition, provide an indication whether a refresh operation of the user data improves performance of the memory component;

receive a user input indicating to perform the refresh operation of the memory component;

determine that a time between the refresh operation and a previously performed refresh operation does not exceed a threshold time; and

determine to not perform the refresh operation of the memory component.

11. A method comprising:

receiving a user input from a user to perform a refresh operation of a memory component;

upon receiving the user input from the user to perform the refresh operation of the memory component, sending an initial translation map to a host system coupled to the memory component;

receiving, from the host system, a modified translation map; and

performing, by a processing device, the refresh operation of the memory component using the modified translation map.

12. The method of claim 11, wherein the initial translation map is configured to map a plurality of logical block addresses (LBAs) to a plurality of physical block addresses using a first order, and wherein the modified translation map is configured to map the plurality of LBAs to the plurality of physical block addresses using a second order that is different from the first order.

13. The method of claim 12, wherein performing the refresh operation of the memory component using the modified translation map comprises:

performing the refresh operation of the memory component using the physical block addresses in the second order.

14. The method of claim 11, wherein performing the refresh operation of the memory component comprises:

erasing user data from a first location of the memory component; and

performing a write operation on a second location of the memory component using the user data.

15. The method of claim 14, wherein performing the write operation on the second location of the memory component comprises:

providing the user data to the host system for storing the user data;

performing the write operation on the second location of the memory component incrementally in a plurality of stages, wherein a portion of the user data is written to the second location in each stage of the plurality of stages; and

upon completion of performing the write operation using the plurality of stages, indicating to the host system to erase the user data from the host system.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

determine a type of settings optimization to perform a refresh operation of a memory component;

determine a refresh operation parameter to use based on the determined type of settings optimization; and

perform the refresh operation of the memory component using the refresh operation parameter.

17. The non-transitory computer-readable storage medium of claim 16, wherein to determine the type of settings optimization, the processing device is to:

identify a workload performed associated with the memory component; and

determine the type of settings optimization based on the identified workload.

18. The non-transitory computer-readable storage medium of claim 17, wherein the identified workload indicates a workload pattern corresponding to one of:

a write intensive workload pattern, or

a read intensive workload pattern.

19. The non-transitory computer-readable storage medium of claim 16, wherein to determine the type of settings optimization, the processing device is to:

receive a user input indicating the type of settings optimization; and

determine the type of settings optimization based on the user input.

20. The non-transitory computer-readable storage medium of claim 16, wherein the type of settings optimization corresponds to one or more of:

performance optimization;

data retention optimization;

endurance optimization;

read intensive optimization;

or

write intensive optimization.

21. The non-transitory computer-readable storage medium of claim 16, wherein the refresh operation parameter comprises one or more of:

a threshold voltage to use for the refresh operation;

a specified level of current to use for the refresh operation;

a specified level of intensity to use for the refresh operation;

a duration of time to use for the refresh operation;

or

a number of passes to use for the refresh operation.

22. The non-transitory computer-readable storage medium of claim 16, wherein to perform the refresh operation of the memory component, the processing device is to:

erase user data from a first location of the memory component; and

perform a write operation on a second location of the memory component based on the user data using the refresh operation parameter.